STC instruction (General-purpose)

STC sets the carry flag and changes nothing else. It is the third of the instructions that work on CF alone, with CLC, which clears it, and CMC, which inverts it; the CLC page covers their common uses, such as reporting a yes or no in CF from assembly and preparing a rotate through CF with RCL or RCR. Zen 5 set CF in each of its six recorded cases, whether it was clear or already set, and left the other flags alone.

A carry of 1 into a chain

An ADC after STC adds one more than an ADD would, so STC starts a carry chain that needs an extra 1 at its bottom, as in a + ~b + 1, the two’s-complement subtraction. GCC 14 and Clang 23 have __builtin_addcl(a, b, carry_in, &carry_out); with a carry-in of 1, GCC at -O2 emits stc and adc rax, rsi, followed by SETC for the carry out, while Clang 23 emits an ADD and an INC and combines their two carries with SETB, SETE and OR. For a 128-bit a + ~b + 1, both recognize the subtraction and emit SUB and SBB, with no STC.

From inline assembly, a flag output operand reads CF directly: stc with the constraint "=@ccc" compiles in both to STC and a SETC (Clang prints SETB).

Cost

STC writes only part of the flags, an instruction that Intel’s optimization manual names among the causes of partial flag register stalls on older processors (Section 3.5.2.5). The instruction table of AMD’s Zen 5 guide lists STC as one macro-op on an ALU, against STD, the direction flag’s set, which is microcoded.

Forms

Every encoding of STC that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`STC` STC	`F9`	Base instruction set

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`STC`
Sandy Bridge	1 / 0.33p015
Haswell, Broadwell, Skylake, Skylake-SP, Ice Lake	1 / 0.25p0156
Alder Lake, Sapphire Rapids	1 / 0.2p0 p1 p5 p6 p11
Lunar Lake	1 / 0.33p135
Bonnell	1 / 0.5p01
Silvermont	1 / 0.5IEC0 IEC1
Piledriver	1 / 1EX0 EX1
Zen, Zen 2, Zen 3, Zen 4	1 / 0.25ALU0 ALU1 ALU2 ALU3
Jaguar	1 / 0.5ALU0 ALU1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

cf = 1

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`STC`
`RFLAGS`	implicit	write

Flags

1 set; blank: not affected. How to read.

CF
All forms
1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I86` General-purpose System	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

A carry of 1 into a chain#

Cost#