STD instruction (General-purpose)

STD sets the direction flag, DF, bit 10 of RFLAGS, and changes no other flag. DF steers the string instructions: while it is set, MOVS, STOS, LODS, CMPS, SCAS, INS and OUTS step RSI and RDI down by the element size after each element instead of up. CLD clears it again. Zen 5 set bit 10 in each of its six recorded cases and left every other flag alone.

Copying backwards

The use for a downward string operation is a copy whose destination overlaps the source at a higher address, as in memmove: copied upward, the first elements written would overwrite source elements not yet read. With DF set, RSI and RDI start at the last element and the copy runs from the top. Intel’s optimization manual warns that this is much slower on its processors than an upward REP MOVS and suggests copying the overlapping tail first instead (Section 3.7.6.3).

Leaving it set

The System V and Microsoft x64 calling conventions require DF to be clear at every call and return (see the registers), and compiled code relies on it: GCC 14 copies a 512-byte struct with a REP MOVS and no CLD before it. Code that runs STD must therefore clear DF again before it calls a function, returns or lets any other code run. Neither GCC 14 nor Clang 23 emitted STD in our builds: an overlapping move became a call to memmove, or, in Clang for a fixed 64 bytes, four vector loads before four stores.

Cost

Intel’s optimization manual lists STD among the instructions that write part of the flags register (Section 3.5.2.5). The instruction table of AMD’s Zen 5 guide lists STD and CLD as microcoded, while STC and CLC are single macro-ops.

Forms

Every encoding of STD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`STD` STD	`FD`	Base instruction set

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`STD`
Sandy Bridge	1 / 0.33p015
Haswell, Broadwell, Skylake, Skylake-SP, Ice Lake	6 / 1.5p0156
Alder Lake, Sapphire Rapids	6 / 0.5p0 p1 p5 p6 p11
Lunar Lake	6 / 0.33p012345
Bonnell	21 / 10.5p01
Silvermont	1 / 0.5IEC0 IEC1
Piledriver	1 / 1EX0 EX1
Zen, Zen 2, Zen 3, Zen 4	1 / 0.25ALU0 ALU1 ALU2 ALU3
Jaguar	1 / 0.5ALU0 ALU1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

df = 1                           # string instructions step rSI and rDI down

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`STD`
`RFLAGS`	implicit	write

Flags

1 set; blank: not affected. How to read.

DF
All forms
1

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction in some cases

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I86` General-purpose System	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

Copying backwards#

Leaving it set#

Cost#