STI instruction (General-purpose)

STI sets IF, the interrupt flag, so that the logical processor accepts maskable external interrupts again after a CLI. It changes no other flag. Like CLI, it has no effect on exceptions or NMIs, which IF never held off.

One instruction later

When STI finds IF clear, interrupts are not taken right after it but only after the next instruction: both manuals describe this window, often called the interrupt shadow. It makes two sequences safe:

STI then HLT. An idle loop can check for work with interrupts off and then run sti; hlt; no interrupt can slip in between the two, so none is missed before the processor sleeps (see HLT).
STI then a return. Enabling interrupts as the last thing before a RET or a jump lets that instruction complete first.

STI followed at once by CLI therefore lets no interrupt in at all, as AMD’s manual points out. Intel’s adds that NMIs and SMIs may be held off on the same instruction boundary, and that the window also ends when another event, such as an exception, is delivered. When IF is already set, STI changes nothing and opens no window.

Who may run it

STI is I/O-sensitive: it sets IF when CPL is at most IOPL. Otherwise, at CPL 3 with CR4.PVI set, it sets VIF instead, unless VIP shows a virtual interrupt pending, where it raises #GP(0) so that the operating system can deliver that interrupt; in all other cases it raises #GP(0). AMD’s manual and Intel’s decision table and Operation section agree on the VIP case, while the Description section of Intel’s revision 093 states it the other way round. The probe runs at CPL 3 with IOPL 0, and there Zen 5 raised #GP in each of its three recorded cases, with RFLAGS unchanged.

POPF and IRET can also set IF, under the same privilege rule but without faulting. The instruction table of AMD’s Zen 5 guide lists STI as microcoded.

Forms

Every encoding of STI that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`STI` STI	`FB`	Base instruction set

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`STI`
Sandy Bridge	100 / 0.33p015
Haswell, Broadwell, Skylake, Skylake-SP, Ice Lake	100 / 0.25p0156
Alder Lake, Sapphire Rapids	100 / 2p0 p1 p5 p6 p11
Lunar Lake	100 / 1.33p012345
Bonnell	100 / 0.5p01
Silvermont	100 / 1FPC0
Piledriver	100 / 0.5EX0 EX1
Zen, Zen 2	100 / 0.25
Zen 3, Zen 4	100 / 25ALU0 ALU1 ALU2 ALU3
Jaguar	100 / 0.5ALU0 ALU1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if CPL <= iopl:
    if_ = 1                      # interrupts are taken again once the next
                                 # instruction is done
elif CPL == 3 and cr4 >> 1 & 1:  # CR4.PVI: protected-mode virtual
    if vip:                      # interrupts, VIF in IF's place; #GP(0)
        fault(GP, 0)             # while one is pending (VIP)
    vif = 1
else:
    fault(GP, 0)                 # as in the probe's cases: CPL 3, IOPL 0

Run on AMD Zen 5 (EPYC 9645): 3 cases. Every one raised an exception, at CPL 3, where the probe runs.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`STI`
`RFLAGS`	implicit	read, write

Flags

T tested, M modified; blank: not affected. How to read.

IF	IOPL	VIF
All forms
M	T	M

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I86` General-purpose System	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

One instruction later#

Who may run it#