STMXCSR instruction (SSE)

STMXCSR stores MXCSR, the control and status register of the SSE, AVX and AVX-512 floating-point instructions, to a doubleword in memory. LDMXCSR loads it, and its page lists the fields: the six sticky exception flags, their masks, the rounding mode, DAZ and FTZ. Reading the register is how code learns which exceptions a calculation raised, and saving it is the first half of any change, since there is no instruction that sets one field alone. VSTMXCSR is the VEX form, with the same effect.

Memory only

There is no form with a register destination: the value goes to memory and comes back with a load. Both manuals say that reserved bits are stored as zeros, so bits 31:16 of the doubleword are 0, apart from bit 17 on AMD’s processors, the mask of AMD’s misaligned exception (MM). Zen 5 stored 1F80H, the value after reset, and FFFFH, every bit of the low half, as 00001F80H and 0000FFFFH.

AMD’s table of the MXCSR flags that STMXCSR affects marks every one as possibly modified, the same table as for LDMXCSR, while its text and Intel’s only store the register; in both recorded cases MXCSR was left as it was.

From C

_mm_getcsr() compiles in GCC 14 and Clang 23 at -O2 to STMXCSR into the red zone below RSP, then a load of the doubleword into EAX. _MM_GET_ROUNDING_MODE() and _MM_GET_FLUSH_ZERO_MODE() add an AND with 6000H and 8000H, and with -mavx all three use VSTMXCSR. To test the exception flags, AND the value with 3FH; to clear them, store, clear bits 5:0 and load back: unlike the x87’s FNCLEX, no instruction clears them alone. FXSAVE and XSAVE store MXCSR too, at bytes 24 to 27 of their area, next to MXCSR_MASK.

AMD’s Zen 5 guide lists STMXCSR as two macro-ops.

In the optimization guide

What the optimization guide says about STMXCSR, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

Denormals, FTZ and DAZ: Writing MXCSR with LDMXCSR serializes the processor and reading it is slow, so FTZ and DAZ are best set once.

Forms

Every encoding of STMXCSR that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`STMXCSR m32` STMXCSR_MEMd	`NP 0F AE /3`	SSE

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

dest.write(mxcsr)                    # the bits it lacks as zeros

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`STMXCSR m32`
`m32`	explicit	write
`MXCSR`	implicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_5

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSEMXCSR` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

Memory only#

From C#