x86-64.net

Instruction

STOS

Stores AL, AX, EAX or RAX at [RDI] and steps RDI; REP STOS fills RCX elements, the classic memset.

Extensions
Mnemonics
STOS, STOSB, STOSW, STOSD, STOSQ
Forms
8 (8 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of STOS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
STOSB STOSBAABase instruction set
STOSW STOSW66 ABBase instruction set
STOSD STOSDABBase instruction set
STOSQ 64-bit mode only STOSQREX.W ABLM
REP STOSB REP_STOSBF3 AA
F2 AA		Base instruction set
REP STOSW REP_STOSW66 F3 AB
66 F2 AB		Base instruction set
REP STOSD REP_STOSDF3 AB
F2 AB		Base instruction set
REP STOSQ 64-bit mode only REP_STOSQF3 REX.W AB
F2 REX.W AB		LM

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
I86

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
I386

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
LONGMODE

LM
CPUID.80000001H:EDX[29] LM

Every x86-64 processor in XED’s model

More General-purpose instructions

All 109 General-purpose instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.