STR instruction (System)

STR stores the selector in the task register, TR: the GDT selector of the task state segment that LTR loaded. Only the 16-bit selector comes out, not the base or limit that TR caches from the descriptor; code that needs the TSS’s address reads the descriptor in the GDT, whose base SGDT gives. It is the task-register counterpart of SLDT.

Operand sizes

Memory: always a 16-bit store, whatever the operand size.
A register: the selector is zero-extended to the operand size. Intel’s text says this of 32-bit and 64-bit registers; AMD’s lists 16-, 32- and 64-bit registers. A 32-bit destination clears bits 63:32 too, as any write of a 32-bit register does in 64-bit mode.

Privilege

STR is not privileged in either manual: it runs at any CPL in protected and long mode, and raises #UD in real and virtual-8086 mode. With UMIP, CR4 bit 11, it raises #GP(0) at CPL above 0, as SGDT, SIDT, SLDT and SMSW do; the SGDT page explains the feature.

The probe does not run STR, for the reasons its Operation section gives. Neither GCC 14 nor Clang 23 has an intrinsic for it. AMD’s Zen 5 guide lists STR as microcoded.

Forms

Every encoding of STR that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`STR m16` STR_MEMw	`0F 00 /1`	Base instruction set
`STR r16/32/64` STR_GPRv	`0F 00 /1`	Base instruction set

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if CPL > 0 and cr4 >> 11 & 1:    # CR4.UMIP
    fault(GP, 0)                 # Linux 7.2 emulates it: 40H,
                                 # leaving bits 63:32 of a 32-bit
                                 # register as they were
dest.write(tr)                   # the TSS's selector: memory, 16 bits
                                 # at any operand size; a register of
                                 # 32 or 64 bits, zero-extended

Not run on a processor: at CPL 3 with CR4.UMIP set, as Linux sets it, STR raises #GP(0), and Linux 7.2 emulates it for programs with made-up values.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`STR m16`
`m16`	explicit	write
`TR`	implicit	read
`STR r16/32/64`
`r16/32/64`	explicit	write
`TR`	implicit	read

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms: not in real-address mode; may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I286PROTECTED` System	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

STR

Operand sizes

Privilege

Forms

Operation

Operands

Flags

Attributes

CPUID and processors

More System instructions

Sources

Operand sizes#

Privilege#

Forms

Operation

Operands

Flags

Attributes

CPUID and processors

More System instructions

Sources

Operand sizes

Privilege