x86-64.net

Instruction

STTILECFG

Stores the current AMX tile configuration to a 64-byte memory block.

Extensions
Forms
2 (1 VEX, 1 EVEX)
Data
Intel XED v2026.08.23

STTILECFG writes the current AMX tile configuration to 64 bytes of memory, in the format that LDTILECFG reads and its page shows: the palette in byte 0, start_row in byte 1, the bytes per row of each tile from byte 16 and the rows of each tile from byte 48, with zero in every reserved byte and for every tile the palette does not have. With no configuration loaded, after a reset or TILERELEASE, it writes 64 zero bytes, which LDTILECFG accepts back as palette 0. Under ACE’s palette 2, whose tile shapes are fixed, only byte 0 is nonzero. No flag changes.

Saving and restoring

The pair lets code that does not own the tiles keep someone else’s configuration: store it, load its own, and reload the stored one later. Since LDTILECFG clears all tile data, this keeps only the shapes; the data needs XSAVE or tile stores. The start_row byte matters here: a tile load or store interrupted by an exception records in it the row to resume from, and an operating system that switches tasks saves it with the rest of the tile state through XSAVE.

Checks

STTILECFG raises #UD unless CR4.OSXSAVE is set, XCR0 enables the tile state (bits 18:17) and the processor is in 64-bit mode, and for VEX.vvvv other than all ones; the store itself can raise #GP for a non-canonical address, #SS and #PF. It needs no loaded configuration, raises no #NM when IA32_XFD disables the tiles, and aborts a TSX transaction. APX adds an EVEX form for its new registers.

Not run here

Zen 5 has no AMX, so the probe left STTILECFG unrun, as it did the APX form. GCC 14 and Clang 23 compile _tile_storeconfig(p) with -mamx-tile to a single STTILECFG, VEX.128.66.0F38.W0 49 /0, using a RIP-relative address for a global buffer.

Forms

Every encoding of STTILECFG that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
STTILECFG m512 64-bit mode only STTILECFG_MEMVEX.128.66.0F38.W0 49 /0ACE v1 or AMX_TILE
STTILECFG m512 STTILECFG_MEM_APXEVEX.128.66.0F38.W0 49 /0ACE v1 or APX_F + AMX_TILE

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelm512
Sapphire Rapids100 / 0.25p0156

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

on = xcr0 if cr4 >> 18 & 1 else 0    # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 3 != 3:                # TILECFG and TILEDATA
    fault(UD)
mem.write(tilecfg)                   # 64 zeros with no configuration,
                                     # palette 2's byte and zeros
# IA32_XFD does not stop it (no #NM)

Not run on a processor: none of these processors has AMX.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
STTILECFG m512 64-bit mode only
m512explicitwrite

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
AMX-E2
EVEX forms
AMX-E2-EVEX

Attributes

What else XED records about the forms. How to read.

All forms
may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to STTILECFG, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_tile_storeconfig void _tile_storeconfig(void *__config)

STTILECFG m512 VEX.128 -mamx-tile

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AMX_TILE_BASE

ACE v1
CPUID.(EAX=07H,ECX=1):ECX[11] ACE
CPUID.(EAX=1DH,ECX=2):EAX[7:0] ≥ 1 ACE version

or

AMX_TILE
CPUID.(EAX=07H,ECX=0):EDX[24] AMX_TILE

Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
APX_F_AMX_BASE

ACE v1
CPUID.(EAX=07H,ECX=1):ECX[11] ACE
CPUID.(EAX=1DH,ECX=2):EAX[7:0] ≥ 1 ACE version

or

APX_F + AMX_TILE
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=07H,ECX=0):EDX[24] AMX_TILE

Diamond Rapids

More AMX-TILE instructions

More ACE instructions

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-682 (STTILECFG)
  5. x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026)
  6. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 9.0 (355828-009, August 2026)
  7. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.