Extensions
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

STUI sets the user-interrupt flag, UIF, so that user interrupts can be delivered again; CLUI clears it and TESTUI reads it. UIF does for user interrupts what IF does for ordinary ones, but it belongs to the program: all three instructions work at CPL 3, and no operating-system setting restricts them beyond turning user interrupts on with CR4.UINTR.

No delay

A user interrupt that is pending can be delivered right after STUI, on the very next instruction boundary. STI behaves otherwise: ordinary interrupts stay blocked until the instruction after it has completed. Code that allows user interrupts again must therefore have its state in order before the STUI itself. Intel’s manual also notes that STI’s one-instruction window does not hold back user interrupts.

Delivery clears UIF on its own, so a handler runs with user interrupts blocked; a handler can execute STUI to let another user interrupt interrupt it, and UIRET sets UIF again on the way out.

Restoring a saved state

GCC 14 and Clang 23 with -muintr at -O2 compile _stui() to stui. For a section that must not be interrupted, the usual pattern saves the flag with _testui(), clears it with _clui() and sets it again afterwards only if it was set: both compilers made TESTUI, a SETcc of CF, CLUI, the protected code, and a test that branches around the STUI.

Where it runs

STUI exists only in 64-bit mode, needs UINTR (CPUID leaf 7, EDX bit 5) and CR4.UINTR, and raises #UD otherwise or with a LOCK prefix. In a TSX transaction it aborts the transaction as STI would. Its bytes, F3 0F 01 EF, are those of WRPKRU with an F3 prefix; the probe does not run them, as the Operation section says, so the site has no Zen 5 result for STUI.

Forms

Every encoding of STUI that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
STUI 64-bit mode only STUIF3 0F 01 EFUINTR

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
ModelSTUI
Sapphire Rapids100 / 0.25p0156

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cr4 >> 25 & 1:            # CR4.UINTR; clear without UINTR
    fault(UD)
uif = 1                          # at once: a pending user interrupt
                                 # may be delivered right after it,
                                 # not one instruction later as an
                                 # interrupt after STI

Not run on a processor: its bytes are WRPKRU's with an F3 prefix, which a processor without UINTR may run as WRPKRU, so that a case would not record STUI; and no processor at hand has UINTR.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
STUI 64-bit mode only
UIFimplicitwrite

Flags

None: XED records no flag that the forms test or change.

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to STUI, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_stui void _stui(void)

STUI Legacy -muintr

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
UINTR

UINTR
CPUID.(EAX=07H,ECX=0):EDX[5] UINTR

Arrow Lake, Panther Lake, Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest

More UINTR instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-684 (STUI)
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3 (325384-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.