x86-64.net

Instruction

SUB

Subtracts one integer from another and sets the arithmetic flags; APX adds three-operand forms and forms that leave the flags unchanged.

Extensions
Forms
60 (24 Legacy, 36 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of SUB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
SUB m8, imm8 SUB_MEMb_IMMb_80r580 /5 ibBase instruction set
SUB r8, imm8 SUB_GPR8_IMMb_80r580 /5 ibBase instruction set
SUB m16/32/64, imm16/32 SUB_MEMv_IMMz81 /5 iw/idBase instruction set
SUB r16/32/64, imm16/32 SUB_GPRv_IMMz81 /5 iw/idBase instruction set
SUB m8, imm8 not in 64-bit mode SUB_MEMb_IMMb_82r582 /5 ibBase instruction set
SUB r8, imm8 not in 64-bit mode SUB_GPR8_IMMb_82r582 /5 ibBase instruction set
SUB m16/32/64, imm8 SUB_MEMv_IMMb83 /5 ibBase instruction set
SUB r16/32/64, imm8 SUB_GPRv_IMMb83 /5 ibBase instruction set
SUB m8, r8 SUB_MEMb_GPR828 /rBase instruction set
SUB r8, r8 SUB_GPR8_GPR8_2828 /rBase instruction set
SUB m16/32/64, r16/32/64 SUB_MEMv_GPRv29 /rBase instruction set
SUB r16/32/64, r16/32/64 SUB_GPRv_GPRv_2929 /rBase instruction set
SUB r8, r8 SUB_GPR8_GPR8_2A2A /rBase instruction set
SUB r8, m8 SUB_GPR8_MEMb2A /rBase instruction set
SUB r16/32/64, r16/32/64 SUB_GPRv_GPRv_2B2B /rBase instruction set
SUB r16/32/64, m16/32/64 SUB_GPRv_MEMv2B /rBase instruction set
SUB AL, imm8 SUB_AL_IMMb2C ibBase instruction set
SUB rAX, imm16/32 SUB_OrAX_IMMz2D iw/idBase instruction set
LOCK SUB m8, imm8 SUB_LOCK_MEMb_IMMb_80r580 /5 ibBase instruction set
LOCK SUB m16/32/64, imm16/32 SUB_LOCK_MEMv_IMMz81 /5 iw/idBase instruction set
LOCK SUB m8, imm8 not in 64-bit mode SUB_LOCK_MEMb_IMMb_82r582 /5 ibBase instruction set
LOCK SUB m16/32/64, imm8 SUB_LOCK_MEMv_IMMb83 /5 ibBase instruction set
LOCK SUB m8, r8 SUB_LOCK_MEMb_GPR828 /rBase instruction set
LOCK SUB m16/32/64, r16/32/64 SUB_LOCK_MEMv_GPRv29 /rBase instruction set
SUB r8, r8 SUB_GPR8i8_GPR8i8_APXEVEX.LLZ.NP.MAP4.WIG 28 /r
EVEX.LLZ.NP.MAP4.WIG 2A /r		APX_F
SUB m8, r8 SUB_MEMi8_GPR8i8_APXEVEX.LLZ.NP.MAP4.WIG 28 /rAPX_F
SUB r8, r8 NF SUB_GPR8i8_GPR8i8_APX_N3EVEX.LLZ.NP.MAP4.WIG 28 /r NF=1
EVEX.LLZ.NP.MAP4.WIG 2A /r NF=1		APX_F + APX_NCI_NDD_NF
SUB m8, r8 NF SUB_MEMi8_GPR8i8_APX_N3EVEX.LLZ.NP.MAP4.WIG 28 /r NF=1APX_F + APX_NCI_NDD_NF
SUB r16/32/64, r16/32/64, imm8 NDD NF optional SUB_GPRv_GPRv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 83 /5 ib ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
SUB r16/32/64, m16/32/64, imm8 NDD NF optional SUB_GPRv_MEMv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 83 /5 ib ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
SUB r8, r8, r8 NDD NF optional SUB_GPR8i8_GPR8i8_GPR8i8_APX_N3EVEX.LLZ.NP.MAP4.WIG 28 /r ND=1 NF=0/1
EVEX.LLZ.NP.MAP4.WIG 2A /r ND=1 NF=0/1		APX_F + APX_NCI_NDD_NF
SUB r8, m8, r8 NDD NF optional SUB_GPR8i8_MEMi8_GPR8i8_APX_N3EVEX.LLZ.NP.MAP4.WIG 28 /r ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
SUB r16/32/64, r16/32/64 SUB_GPRv_GPRv_APXEVEX.LLZ.NP.MAP4.SCALABLE 29 /r
EVEX.LLZ.NP.MAP4.SCALABLE 2B /r		APX_F
SUB m16/32/64, r16/32/64 SUB_MEMv_GPRv_APXEVEX.LLZ.NP.MAP4.SCALABLE 29 /rAPX_F
SUB r16/32/64, r16/32/64 NF SUB_GPRv_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 29 /r NF=1
EVEX.LLZ.NP.MAP4.SCALABLE 2B /r NF=1		APX_F + APX_NCI_NDD_NF
SUB m16/32/64, r16/32/64 NF SUB_MEMv_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 29 /r NF=1APX_F + APX_NCI_NDD_NF
SUB r16/32/64, r16/32/64, r16/32/64 NDD NF optional SUB_GPRv_GPRv_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 29 /r ND=1 NF=0/1
EVEX.LLZ.NP.MAP4.SCALABLE 2B /r ND=1 NF=0/1		APX_F + APX_NCI_NDD_NF
SUB r16/32/64, m16/32/64, r16/32/64 NDD NF optional SUB_GPRv_MEMv_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 29 /r ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
SUB r8, m8 SUB_GPR8i8_MEMi8_APXEVEX.LLZ.NP.MAP4.WIG 2A /rAPX_F
SUB r8, m8 NF SUB_GPR8i8_MEMi8_APX_N3EVEX.LLZ.NP.MAP4.WIG 2A /r NF=1APX_F + APX_NCI_NDD_NF
SUB r8, r8, m8 NDD NF optional SUB_GPR8i8_GPR8i8_MEMi8_APX_N3EVEX.LLZ.NP.MAP4.WIG 2A /r ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
SUB r16/32/64, m16/32/64 SUB_GPRv_MEMv_APXEVEX.LLZ.NP.MAP4.SCALABLE 2B /rAPX_F
SUB r16/32/64, m16/32/64 NF SUB_GPRv_MEMv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 2B /r NF=1APX_F + APX_NCI_NDD_NF
SUB r8, r8, imm8 NDD NF optional SUB_GPR8i8_GPR8i8_IMM8_APX_N3EVEX.LLZ.NP.MAP4.WIG 80 /5 ib ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
SUB r8, m8, imm8 NDD NF optional SUB_GPR8i8_MEMi8_IMM8_APX_N3EVEX.LLZ.NP.MAP4.WIG 80 /5 ib ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
SUB r16/32/64, r16/32/64, m16/32/64 NDD NF optional SUB_GPRv_GPRv_MEMv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 2B /r ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
SUB r8, imm8 SUB_GPR8i8_IMM8_APXEVEX.LLZ.NP.MAP4.WIG 80 /5 ibAPX_F
SUB m8, imm8 SUB_MEMi8_IMM8_APXEVEX.LLZ.NP.MAP4.WIG 80 /5 ibAPX_F
SUB r8, imm8 NF SUB_GPR8i8_IMM8_APX_N3EVEX.LLZ.NP.MAP4.WIG 80 /5 ib NF=1APX_F + APX_NCI_NDD_NF
SUB m8, imm8 NF SUB_MEMi8_IMM8_APX_N3EVEX.LLZ.NP.MAP4.WIG 80 /5 ib NF=1APX_F + APX_NCI_NDD_NF
SUB r16/32/64, imm16/32 SUB_GPRv_IMMz_APXEVEX.LLZ.NP.MAP4.SCALABLE 81 /5 iw/idAPX_F
SUB m16/32/64, imm16/32 SUB_MEMv_IMMz_APXEVEX.LLZ.NP.MAP4.SCALABLE 81 /5 iw/idAPX_F
SUB r16/32/64, imm16/32 NF SUB_GPRv_IMMz_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 81 /5 iw/id NF=1APX_F + APX_NCI_NDD_NF
SUB m16/32/64, imm16/32 NF SUB_MEMv_IMMz_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 81 /5 iw/id NF=1APX_F + APX_NCI_NDD_NF
SUB r16/32/64, r16/32/64, imm16/32 NDD NF optional SUB_GPRv_GPRv_IMMz_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 81 /5 iw/id ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
SUB r16/32/64, m16/32/64, imm16/32 NDD NF optional SUB_GPRv_MEMv_IMMz_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 81 /5 iw/id ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
SUB r16/32/64, imm8 SUB_GPRv_IMM8_APXEVEX.LLZ.NP.MAP4.SCALABLE 83 /5 ibAPX_F
SUB m16/32/64, imm8 SUB_MEMv_IMM8_APXEVEX.LLZ.NP.MAP4.SCALABLE 83 /5 ibAPX_F
SUB r16/32/64, imm8 NF SUB_GPRv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 83 /5 ib NF=1APX_F + APX_NCI_NDD_NF
SUB m16/32/64, imm8 NF SUB_MEMv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 83 /5 ib NF=1APX_F + APX_NCI_NDD_NF

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
I86

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
APX_F

APX_F
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F

Nova Lake, Diamond Rapids
APX_F_N3

APX_F + APX_NCI_NDD_NF
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=29H,ECX=0):EBX[0] APX_NCI_NDD_NF

Nova Lake, Diamond Rapids

More General-purpose instructions

All 109 General-purpose instructions

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
  4. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.