SUBPD instruction (SSE2)

SUBPD is SSE2’s subtraction of two doubles: the two of its second operand from the two of its first, the differences replacing the first. VSUBPD is the same operation in VEX and EVEX encodings; its page and VSUBPS’s cover the order of the operands, the sign of a zero difference and the rounding edges, which this form shares. What the legacy encoding has of its own:

Two operands. The first source is also the destination, so code that still needs it copies it first. For a[i] = 1.0 - b[i], Clang 23 in our builds keeps the vector of ones in a register and puts a MOVAPD copy of it before each SUBPD, where VSUBPD would name the ones as its first source and write elsewhere.
The bits above 127 stay. The legacy form writes bits 127:0 and leaves the rest of the YMM or ZMM register as it was, while VSUBPD on an xmm register clears it; Zen 5’s recorded cases kept bits 511:128 in both forms. Code that mixes the two kinds pays for the switch, as the optimization guide’s SSE and AVX section describes.
Aligned memory. A memory operand must sit on a 16-byte boundary, or the instruction raises #GP; VSUBPD takes any address. AMD’s manual lets processors with its misaligned SSE mode accept such operands while MXCSR.MM is set.

On Zen 5, subpd xmm4, xmmword ptr [mem] rounding toward zero gave 1 minus 2^-53 as 0.9999999999999999, exactly, and 1 minus 1.5 times 2^-53, which falls between two doubles, as 1 minus 2^-52, setting PE.

In baseline code

SSE2 is part of every x86-64 processor, so compilers use it without any option. In our builds at -O2, with the default target and with -march=x86-64-v2 alike, Clang 23 compiles a[i] = b[i] - c[i] over pointers to SUBPD between registers, two per iteration, after loading both operands with MOVUPD, since the arrays may not be aligned. GCC 14 keeps that loop scalar, one SUBSD per element; for global arrays of fixed size, which it aligns to 32 bytes, both compilers emit SUBPD with the second operand straight from memory. _mm_sub_pd, or a minus between two __m128d, is one SUBPD.

In the optimization guide

What the optimization guide says about SUBPD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

Zeroing and dependency-breaking idioms: A floating-point subtraction of a register from itself is not a safe way to zero it, since a NaN input gives NaN. sources differ

Forms

Every encoding of SUBPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`SUBPD xmm, m128` SUBPD_XMMpd_MEMpd	`66 0F 5C /r`	SSE2
`SUBPD xmm, xmm` SUBPD_XMMpd_XMMpd	`66 0F 5C /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each double of the result comes from the double in the same place in each source.

Result double i comes from double i of xmm1 and xmm2. Result doubles 1 to 0: a1-b1, a0-b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    a = xmm1.f64[i]
    b = src2.f64[i]
    xmm1.f64[i] = sub(a, b)
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`SUBPD xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_2

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR
Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to SUBPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_sub_pd` `__m128d _mm_sub_pd(__m128d __a, __m128d __b)`	`SUBPD xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

In baseline code#