SUBPS instruction (SSE)

SUBPS subtracts the four singles of its second operand from those of its first. VSUBPS is the VEX and EVEX form, and its page covers the order of the operands, the sign of a zero difference and what compilers make of a minus sign; SUBPD is the double-precision form. This legacy encoding, from the first SSE and so on every x86-64 processor, writes its result over the first operand, leaves bits 128 and up of the register as they were (see SSE and AVX) and needs a memory operand aligned to 16 bytes, or it raises #GP.

Zen 5’s recorded cases:

Under MXCSR’s default, subps xmm12, xmm6 took 2^-24 from 1 exactly; 1 minus 1.5 times 2^-24, a tie, gave the even neighbour, 3F7FFFFEH; 1 minus -2^-24 gave 1; infinity minus -infinity gave infinity. PE was set.
With MXCSR at FFC0H (round toward zero, FTZ and DAZ set), subps xmm0, xmmword ptr [mem] took 10^30 from itself to +0 and infinity from -1 to -infinity. Where both elements were quiet NaNs, 7FC00000H in the register and FFC00000H in memory, the result was the register’s, as Intel’s Volume 1 has it for two quiet NaNs (Table 4-8): the first operand wins. No flag was set.

A copy for every constant minuend

Since the difference overwrites the minuend, a[i] = 1.0f - b[i] costs a register copy per vector. Over global arrays at -O2 for the default target, GCC 14 builds the four ones with MOVSS and shufps xmm1, xmm1, 0 (SHUFPS) and Clang 23 loads them from a constant; then both copy them with MOVAPS before each SUBPS, which reads b[i] from memory. Where the first operand is not needed again there is no copy: b[i] - c[i] is a MOVAPS load and a subtraction from memory, and four adjacent float fields of two structs subtract as one SUBPS between two MOVUPS loads.

AMD’s latency spreadsheet for Zen 5 lists SUBPS like ADDPS: one macro-op on pipes FP2 and FP3, a latency of 2 cycles and two per cycle.

In the optimization guide

What the optimization guide says about SUBPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

Zeroing and dependency-breaking idioms: A floating-point subtraction of a register from itself is not a safe way to zero it, since a NaN input gives NaN. sources differ

Forms

Every encoding of SUBPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`SUBPS xmm, m128` SUBPS_XMMps_MEMps	`NP 0F 5C /r`	SSE
`SUBPS xmm, xmm` SUBPS_XMMps_XMMps	`NP 0F 5C /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each single of the result comes from the single in the same place in each source.

Result single i comes from single i of xmm1 and xmm2. Result singles 3 to 0: a3-b3, a2-b2, a1-b1, a0-b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    a = xmm1.f32[i]
    b = src2.f32[i]
    xmm1.f32[i] = sub(a, b)
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`SUBPS xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_2

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR
Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to SUBPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_sub_ps` `__m128 _mm_sub_ps(__m128 __a, __m128 __b)`	`SUBPS xmm, xmm` Legacy -msse

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

A copy for every constant minuend#