SUBSD instruction (SSE2)

SUBSD subtracts the low double of its source from the low double of its destination and keeps the high double. It is SSE2’s scalar form of SUBPD; SUBSS shows where constants go and what happens to two NaNs, and ADDSS covers what the scalar forms share. GCC 14 and Clang 23 at -O2 compile a - b over double to subsd xmm0, xmm1. Zen 5’s two recorded cases:

With MXCSR at FFC0H (round toward zero, FTZ and DAZ set), 10^300 minus itself, read from memory, gave +0: only rounding toward negative infinity makes such a difference -0, as VSUBPS explains.
Under MXCSR’s default, 1 minus -2^-53 gave 1 and set PE: the exact difference lies halfway between 1 and the next double, and the tie goes to the even one.

In compiled code

Since the memory operand may sit at any address, a subtrahend in an array is read in place: in our builds, 1.0 - da[3] over a global array loads the 1 with MOVSD and subtracts QWORD PTR da[rip+24], eight bytes not aligned to 16.

The fractional part, x - (long)x, is a truncation with CVTTSD2SI, a conversion back with CVTSI2SD, whose page explains the PXOR that GCC puts before it, and a SUBSD.

For the differences of neighbours over global arrays, da[i] = db[i + 1] - db[i] for 1,023 elements, GCC keeps the loop scalar: it loads each element once with MOVSD and keeps it in a register, copied with MOVAPD, for the next difference. Clang vectorizes it with SUBPD, building the shifted pairs with SHUFPD, and finishes the last three elements with SUBSD.

AMD’s latency spreadsheet for Zen 5 lists SUBSD at 2 cycles on pipes FP2 and FP3. The legacy form keeps bits 255:128 (see mixing SSE and AVX), and VSUBSD is the VEX and EVEX form.

Forms

Every encoding of SUBSD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`SUBSD xmm, m64` SUBSD_XMMsd_MEMsd	`F2 0F 5C /r`	SSE2
`SUBSD xmm, xmm` SUBSD_XMMsd_XMMsd	`F2 0F 5C /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low double is computed; the other double comes from xmm1.

Result double 0 is computed from double 0 of xmm1 and xmm2; double 1 is that of xmm1. Result doubles 1 to 0: a1, a0-b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.f64[0] = sub(xmm1.f64[0], src2.f64[0])
# xmm1.q[1] keeps its value
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`SUBSD xmm, xmm/m64`
`xmm`	explicit	read, write
`xmm/m64`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_3

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to SUBSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_sub_sd` `__m128d _mm_sub_sd(__m128d __a, __m128d __b)`	`SUBSD xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

In compiled code#