SUBSS instruction (SSE)

SUBSS subtracts the low single of its source from the low single of its destination and keeps singles 1 to 3 of the destination. It is the scalar form of SUBPS; VSUBPS covers the order of the operands and the sign of a zero difference, and ADDSS what the scalar forms share: the kept elements, the memory operand of four bytes at any alignment, and why keeping the elements adds no wait. GCC 14 and Clang 23 at -O2 compile a - b over float to subss xmm0, xmm1.

Constants on either side

The difference replaces the minuend, which decides what a constant costs. In our builds:

x - 1.0f is one instruction with the constant in memory: SUBSS in GCC, and in Clang an ADDSS of -1, the same operation.
1.0f - x needs the 1 in the destination. Both compilers load it with MOVSS and add a MOVAPS: GCC copies x out of XMM0 before the load, Clang copies the difference into XMM0 after it.
-x is not 0.0f - x, since the two differ for x = +0: both compilers flip the sign bit with XORPS. 0.0f - x stays a SUBSS from a zeroed register, and x - x a SUBSS of XMM0 from itself, as an infinity or a NaN gives a NaN.

Two NaNs on Zen 5

For two NaNs, Intel’s Volume 1 gives an SSE instruction its first operand, quieted if it signals (Table 4-8). Zen 5’s two recorded cases agree:

Under MXCSR’s default, 1F80H, the quiet NaN 7FC00000H minus the quiet NaN FFC00000H left 7FC00000H in the destination and set no flag.
With MXCSR at FFC0H, the signaling NaN 7F812345H minus 7FC12345H from memory gave 7FC12345H, which is the first operand quieted, and set IE.

AMD’s latency spreadsheet for Zen 5 lists SUBSS with ADDSS’s figures, 2 cycles on pipes FP2 and FP3. The legacy form keeps bits 255:128 (see mixing SSE and AVX); SUBSD is the double form and VSUBSS the VEX and EVEX one.

Forms

Every encoding of SUBSS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`SUBSS xmm, m32` SUBSS_XMMss_MEMss	`F3 0F 5C /r`	SSE
`SUBSS xmm, xmm` SUBSS_XMMss_XMMss	`F3 0F 5C /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low single is computed; the other singles come from xmm1.

Result single 0 is computed from single 0 of xmm1 and xmm2; singles 3 to 1 are those of xmm1. Result singles 3 to 0: a3, a2, a1, a0-b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.f32[0] = sub(xmm1.f32[0], src2.f32[0])
# xmm1.d[1] to [3] keep their values
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`SUBSS xmm, xmm/m32`
`xmm`	explicit	read, write
`xmm/m32`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_3

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to SUBSS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_sub_ss` `__m128 _mm_sub_ss(__m128 __a, __m128 __b)`	`SUBSS xmm, xmm` Legacy -msse

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

Constants on either side#

Two NaNs on Zen 5#