T1MSKC instruction (TBM)

Forms

Every encoding of T1MSKC that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`T1MSKC r32, m32` not in 64-bit mode T1MSKC_GPR32d_MEMd	`XOP.LZ.NP.09.WIG 01 /7`	TBM
`T1MSKC r32/64, m32/64` 64-bit mode only T1MSKC_GPRyy_MEMy	`XOP.LZ.NP.09.WIG 01 /7`	TBM
`T1MSKC r32, r32` not in 64-bit mode T1MSKC_GPR32d_GPR32d	`XOP.LZ.NP.09.WIG 01 /7`	TBM
`T1MSKC r32/64, r32/64` 64-bit mode only T1MSKC_GPRyy_GPRyy	`XOP.LZ.NP.09.WIG 01 /7`	TBM

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`r32/64, m32/64`	`r32/64, r32/64`
Piledriver	6 / 1.5EX0 EX1	2 / 1EX0 EX1
Zen	5 / 0.5ALU0 ALU1 ALU2 ALU3	1 / 0.25ALU0 ALU1 ALU2 ALU3
Zen 2	5 / 0.33ALU0 ALU1 ALU2 ALU3	1 / 0.25ALU0 ALU1 ALU2 ALU3

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

features = cpuid_leaf(0x80000001, 0)[2]
if not features >> 21 & 1:
    fault(UD)                    # CPUID: no TBM
s = src.read()
t = s + 1
r = low(~s | t)                  # zeros for the trailing 1 bits, ones
                                 # above them
cf = t >> OSIZE                  # 1 when src is all ones
sf = msb(r)
zf = r == 0
of = 0
af = pf = UNDEFINED
dest.write(r)                    # a 32-bit register: bits 63:32 cleared

Run on AMD Zen 5 (EPYC 9645): 4 cases. Its cases ran where CPUID reported no TBM, and every one raised an exception. The forms that 64-bit mode lacks were not run: the probe runs in 64-bit mode.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`T1MSKC r32, r/m32` not in 64-bit mode `T1MSKC r32/64, r/m32/64` 64-bit mode only
`r32/64`	explicit	write
`r/m32/64`	explicit	read
`RFLAGS`	implicit	write

Flags

M modified, 0 cleared, U undefined; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF
All forms
0	M	M	U	U	M

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to T1MSKC, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`__t1mskc_u32` `unsigned int __t1mskc_u32(unsigned int __a)`	`T1MSKC r32/64, r32/64` XOP.LZ -mtbm
`__t1mskc_u64` `unsigned long long __t1mskc_u64(unsigned long long __a)`	`T1MSKC r32/64, r32/64` XOP.LZ -mtbm

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`TBM` TBM	TBM `CPUID.80000001H:ECX[21]` TBM	Piledriver, Zen, Zen+, Zen 2 Note: XED's Zen chips inherit TBM from its Piledriver chip; GCC's -march=znver1 and later do not enable TBM.

T1MSKC