Instruction
TCMMRLFP16PS
Multiplies two tiles of complex half-precision numbers and accumulates the real parts of the products into a single-precision tile.
- Extensions
- Forms
- 1 (1 VEX)
- Data
- Intel XED v2026.08.23
TCMMRLFP16PS multiplies two tiles of complex numbers as matrices and adds the real parts of the result to a tile of singles: C += Re(A × B). Each dword of A and B is one complex number, its real part in the low FP16 half and its imaginary part in the high half, the layout VFMULCPH uses in vector registers. Element C[m][n] gains the sum over k of Ar × Br - Ai × Bi, taking A[m][k] and B[k][n]. TCMMIMFP16PS adds the imaginary parts, Ai × Br + Ar × Bi, so a complex matrix product takes the two instructions and two accumulator tiles. Both came with AMX-COMPLEX, which Intel’s extensions reference lists for Granite Rapids D and Diamond Rapids.
No interleaving in B
The real AMX multiplies, such as TDPFP16PS, read each dword of B as two values from consecutive rows, so B must be repacked first. Here a dword of B is a single complex number, and B is an ordinary row-major matrix of K rows of N complex numbers, as is A. With full tiles of 16 rows of 64 bytes, one instruction makes 16 × 16 sums of 16 complex products each. The shapes are checked as for the other AMX multiplies: A’s dwords per row must equal B’s rows, C must have A’s rows and B’s row width, and #UD follows if they do not fit.
Two sums, then one subtraction
The SDM’s Operation keeps two single-precision sums for each element of C: one of the products of the real parts and one of the products of the imaginary parts, the latter with A’s imaginary part negated. Each product of two FP16 values fits a single exactly, so each step of a sum rounds once, to nearest even. The two sums are added at the end of the row, and the total is added to C. MXCSR is neither read nor written, no exception is raised, FP16 denormals count as the numbers they are, and a denormal single result becomes zero.
In our builds
With -mamx-complex, GCC 14 and Clang 23 at -O2 compile
_tile_cmmrlfp16ps(3, 4, 5) to tcmmrlfp16ps tmm3, tmm4, tmm5, the
bytes C4 E2 50 6C DC, VEX opcode 6Ch with no prefix bits. Clang 23 also
has __tile_cmmrlfp16ps for its __tile1024i type. Zen 5 has no AMX,
and this site’s recorded cases include none of TCMMRLFP16PS.
Forms
| Instruction | Encoding | Requires |
|---|---|---|
TCMMRLFP16PS tmm, tmm, tmm 64-bit mode only
TCMMRLFP16PS_TMMf32_TMM2f16_TMM2f16 | VEX.LZ.NP.0F38.W0 6C /r | AMX_COMPLEX (leaf 1EH) or AMX_COMPLEX |
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
on = xcr0 if cr4 >> 18 & 1 else 0 # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 3 != 3: # TILECFG and TILEDATA
fault(UD)
if palette != 1: # 0: no tiles configured; ACE's
fault(UD) # palette 2 multiplies no tiles
t = tmm1.number # three different tiles
if t == tmm2.number or t == tmm3.number:
fault(UD)
if tmm2.number == tmm3.number:
fault(UD)
if 0 in (tmm1.rows, tmm2.rows, tmm3.rows):
fault(UD) # one TILECFG leaves out
if tmm1.colsb % 4 or tmm2.colsb % 4:
fault(UD) # rows of whole dwords
if tmm2.rows != tmm1.rows: # A: M rows, as C
fault(UD)
if tmm2.colsb // 4 != tmm3.rows: # A: K dwords, B: K rows
fault(UD)
if tmm3.colsb != tmm1.colsb: # B: N dwords, as C
fault(UD)
# K and N within the TMUL unit's 16 and 64 bytes (CPUID leaf
# 1EH): true of every tile of palette 1
if xfd >> 18 & 1: # the OS keeps the tiles from
fault(NM) # this thread
for m in range(tmm1.rows):
x = tmm2.row[m] # row m of A
for n in range(tmm1.colsb // 4):
e = o = cvt_f32_ne(0) # two sums, from +0
for k in range(tmm2.colsb // 4):
y = tmm3.row[k] # row k of B
# re * re, and -im * im
a = x.f16[2 * k]
b = y.f16[2 * n]
e = fmadd_ne(a, b, e)
a = neg(x.f16[2 * k + 1])
b = y.f16[2 * n + 1]
o = fmadd_ne(a, b, o)
c = tmm1.row[m].f32[n]
r = add_ne(e, o)
tmm1.row[m].f32[n] = add_ne(c, r)
start_row = 0
# tmm1 is zeroed past its rows and colsbNot run on a processor: none of these processors has AMX.
Operands
| Operand | Kind | Action |
|---|---|---|
TCMMRLFP16PS tmm, tmm, tmm 64-bit mode only | ||
tmm | explicit | read, write |
tmm | explicit | read |
tmm | explicit | read |
Flags
None: XED records no flag that the forms test or change.
Exceptions
The exception class is XED's name for the set of exception conditions that a form follows. How to read.
- All forms
AMX-E4
Attributes
What else XED records about the forms. How to read.
- All forms
- may abort a TSX transaction
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to TCMMRLFP16PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_tile_cmmrlfp16ps
void _tile_cmmrlfp16ps(const int dst, const int a, const int b) |
Clang's comment names TCMMIMFP16PS, which computes the imaginary parts; this intrinsic computes the real parts, and Clang emits TCMMRLFP16PS. |
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
AMX_COMPLEX | AMX_COMPLEX (leaf 1EH) or AMX_COMPLEX | Granite Rapids, Diamond Rapids |
More AMX-COMPLEX instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-712 (TCMMIMFP16PS/
TCMMRLFP16PS) - Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.