TCVTROWD2PS

TCVTROWD2PS moves one row of a tile into a ZMM register as TILEMOVROW does and turns its dwords, read as signed integers, into singles. TILEMOVROW’s page covers the row number, in bits 3:0 of a register or an immediate, and the faults. A row past the tile’s rows gives a zero register, and elements past the row’s width are zeros too, which here means dwords that are +0.0 singles.

Rounding without MXCSR#

Rounding is always to nearest even, and MXCSR is neither read nor written, nor can an exception be raised. There is no embedded rounding either, unlike VCVTDQ2PS, which follows MXCSR.RC or an EVEX rounding override and flags inexact results. A dword with more than 24 significant bits loses its low bits silently: 2^24 + 1 becomes 2^24 (4B800000H), 2^31 - 1 becomes 2^31 (4F000000H), and -1 becomes BF800000H. Every 32-bit integer has a single within range, so overflow cannot occur. There is no unsigned form: a dword from a tile of unsigned sums, as TDPBUUD leaves, with its top bit set comes out negative.

After an integer multiply, the 32-bit sums of a TDPBSSD can thus leave the tile one row at a time as singles, ready for vector code to scale, without going through memory as with TILESTORED.

In our builds#

GCC 14 has no -mamx-avx512 option. With it, Clang 23 at -O2 compiles _tile_cvtrowd2ps(2, r) to tcvtrowd2ps zmm0, tmm2, edi, and a constant row number moves to a register first, as for TILEMOVROW; _tile_cvtrowd2psi(2, 3) gives the immediate form. __tile_cvtrowd2ps, given a __tile1024i, writes and loads a tile configuration, loads the tile with TILELOADD and then converts. The register form, with ZMM1 and TMM2 and ECX, is 62 F2 76 48 4A CA: opcode 4Ah with the F3 prefix bits, where TILEMOVROW has 66. Under ACE it has that specification’s own exception classes and reads a full row. Zen 5 has no AMX, and this site’s recorded cases include none of TCVTROWD2PS.

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

on = xcr0 if cr4 >> 18 & 1 else 0    # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 3 != 3:                # TILECFG and TILEDATA
    fault(UD)
if on & 0xE6 != 0xE6:                # AVX-512's state, AVX's and
    fault(UD)                        # SSE's
if palette == 0 or not tmm2.rows:    # no configuration, or a tile it
    fault(UD)                        # leaves out
if tmm2.colsb % 4:                   # whole dwords
    fault(UD)
if cr0 >> 3 & 1 or xfd >> 18 & 1:    # CR0.TS, or the OS keeps the
    fault(NM)                        # tiles from this thread
# ACE's exception class for these forms asks for XCR0 bit 20
# (SCALEDATA) too
r = src3 & 15                        # bits 3:0 of imm8 or r32
x = tmm2.row[r]
n = tmm2.colsb // 4 if r < tmm2.rows else 0
for i in range(16):
    if i < n:
        zmm1.f32[i] = cvt_f32_ne(x.sd[i])
    else:                            # past the tile's rows or colsb
        zmm1.d[i] = 0
start_row = 0

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

TCVTROWD2PS zmm, tmm, r32 64-bit mode only

AMX-E8-EVEX

TCVTROWD2PS zmm, tmm, imm8 64-bit mode only

AMX-E7-EVEX

Attributes

What else XED records about the forms. How to read.

All forms

may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to TCVTROWD2PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AMX-AVX512 instructions

• TCVTROWPS2BF16H
• TCVTROWPS2BF16L
• TCVTROWPS2PHH
• TCVTROWPS2PHL
• TILEMOVROW

More ACE instructions

• BSRINIT
• BSRMOVF
• BSRMOVH
• BSRMOVL
• LDTILECFG
• STTILECFG
• TCVTROWPS2BF16H
• TCVTROWPS2BF16L
• TCVTROWPS2PHH
• TCVTROWPS2PHL
• TILEMOVCOL
• TILEMOVROW
• TILERELEASE
• TILEZERO
• TOP2BF16PS
• TOP4BSSD
• TOP4BSUD
• TOP4BUSD
• TOP4BUUD
• TOP4MXBF8PS
• TOP4MXBHF8PS
• TOP4MXBSSPS
• TOP4MXHBF8PS
• TOP4MXHF8PS