TCVTROWPS2BF16H

TCVTROWPS2BF16H moves one row of singles from a tile into a ZMM register as TILEMOVROW does and rounds each to bfloat16, which goes in the high half of its dword; the low half is zero. TCVTROWPS2BF16L puts it in the low half instead. So 16 singles stay 16 dwords, unlike VCVTNEPS2BF16, which packs them into half a register. As in TILEMOVROW, a row past the tile’s rows gives a zero register, and elements past the row’s width are zero dwords.

The rounding#

A bfloat16 number is the upper 16 bits of a single, so the conversion drops the low 16 bits, always rounding to nearest even: 1 + 2^-8 (3F808000H) is a tie and gives 3F80H, 1 + 3 × 2^-8 (3F818000H) gives 3F82H, and -pi (C0490FDBH) gives C049H. The largest single rounds up to +infinity (7F80H). A denormal single becomes a zero of its sign, such as 80000001H to 8000H, and an infinity stays one. A NaN keeps its upper bits and is made quiet: the signaling 7F800001H gives 7FC0H. MXCSR is neither read nor written and nothing is flagged, and there is no embedded rounding.

Pairs for the next multiply#

A zero half makes a row easy to merge. TDPBF16PS wants two consecutive rows of its B interleaved in pairs, and that is what a bitwise OR of a TCVTROWPS2BF16L of one row with a TCVTROWPS2BF16H of the next produces, element by element. VCVTNE2PS2BF16 packs two sources one after the other rather than pairing them, so it does not give that layout.

In our builds#

GCC 14 has no -mamx-avx512 option. With it and -mavx512bf16, Clang 23 at -O2 compiles _tile_cvtrowps2bf16h(2, r) to tcvtrowps2bf16h zmm0, tmm2, edi; _tile_cvtrowps2bf16hi(2, 1) gives the immediate form, whose bytes for ZMM1 and TMM2 are 62 F3 7F 48 07 CA 01. An OR of the two immediate intrinsics on rows 0 and 1 came out as TCVTROWPS2BF16L, TCVTROWPS2BF16H and VORPS. Zen 5 has no AMX, and this site’s recorded cases include none of TCVTROWPS2BF16H.

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

on = xcr0 if cr4 >> 18 & 1 else 0    # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 3 != 3:                # TILECFG and TILEDATA
    fault(UD)
if on & 0xE6 != 0xE6:                # AVX-512's state, AVX's and
    fault(UD)                        # SSE's
if palette == 0 or not tmm2.rows:    # no configuration, or a tile it
    fault(UD)                        # leaves out
if tmm2.colsb % 4:                   # whole dwords
    fault(UD)
if cr0 >> 3 & 1 or xfd >> 18 & 1:    # CR0.TS, or the OS keeps the
    fault(NM)                        # tiles from this thread
# ACE's exception class for these forms asks for XCR0 bit 20
# (SCALEDATA) too
r = src3 & 15                        # bits 3:0 of imm8 or r32
x = tmm2.row[r]
n = tmm2.colsb // 4 if r < tmm2.rows else 0
for i in range(16):
    if i < n:
        v = to_bf16_ne(x.f32[i])
        zmm1.d[i] = v << 16          # the low half 0
    else:                            # past the tile's rows or colsb
        zmm1.d[i] = 0
start_row = 0

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

TCVTROWPS2BF16H zmm, tmm, r32 64-bit mode only

AMX-E8-EVEX

TCVTROWPS2BF16H zmm, tmm, imm8 64-bit mode only

AMX-E7-EVEX

Attributes

What else XED records about the forms. How to read.

All forms

may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to TCVTROWPS2BF16H, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AMX-AVX512 instructions

• TCVTROWD2PS
• TCVTROWPS2BF16L
• TCVTROWPS2PHH
• TCVTROWPS2PHL
• TILEMOVROW

More ACE instructions

• BSRINIT
• BSRMOVF
• BSRMOVH
• BSRMOVL
• LDTILECFG
• STTILECFG
• TCVTROWD2PS
• TCVTROWPS2BF16L
• TCVTROWPS2PHH
• TCVTROWPS2PHL
• TILEMOVCOL
• TILEMOVROW
• TILERELEASE
• TILEZERO
• TOP2BF16PS
• TOP4BSSD
• TOP4BSUD
• TOP4BUSD
• TOP4BUUD
• TOP4MXBF8PS
• TOP4MXBHF8PS
• TOP4MXBSSPS
• TOP4MXHBF8PS
• TOP4MXHF8PS