TCVTROWPS2BF16L

TCVTROWPS2BF16L moves one row of singles from a tile into a ZMM register and rounds each to bfloat16, as TCVTROWPS2BF16H does, but puts the result in the low half of its dword and zeros the high half. That page covers the rounding, always to nearest even, and the treatment of denormals and NaNs; TILEMOVROW’s covers the row number and the faults.

Same conversion, different place#

Each result is the H form’s result shifted right by 16 bits: 1 + 2^-8 as a single gives 00003F80H, and an out-of-range row or an element past the row’s width gives a zero dword in either form. The low half is the even-numbered word of a dword, and it is also where the even-numbered elements of a bfloat16 pair sit. In a TDPBF16PS source, the lower row of two interleaved rows of B goes there, so this instruction converts that row and the H form its neighbour.

Used alone, the L form leaves each number in the low 16 bits of a dword with zeros above it, which is what a later word-level narrowing such as VPMOVDW needs: it packs 16 dwords’ low words into a YMM register, the layout VCVTNEPS2BF16 gives directly from a ZMM register.

Two opcodes#

The register form is EVEX opcode 6Dh of map 0F38 with the F3 prefix bits, one prefix away from the H form’s F2. The immediate form has opcode 77h of map 0F3A with F3, where the H form has 07h with F2: tcvtrowps2bf16l zmm1, tmm2, 1 is 62 F3 7E 48 77 CA 01.

In our builds#

GCC 14 has no -mamx-avx512 option. With it and -mavx512bf16, Clang 23 at -O2 compiles _tile_cvtrowps2bf16l(2, 1) with a constant row through a register, mov eax, 1 and tcvtrowps2bf16l zmm0, tmm2, eax; _tile_cvtrowps2bf16li(2, 1) gives the immediate form. Zen 5 has no AMX, and this site’s recorded cases include none of TCVTROWPS2BF16L.

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

on = xcr0 if cr4 >> 18 & 1 else 0    # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 3 != 3:                # TILECFG and TILEDATA
    fault(UD)
if on & 0xE6 != 0xE6:                # AVX-512's state, AVX's and
    fault(UD)                        # SSE's
if palette == 0 or not tmm2.rows:    # no configuration, or a tile it
    fault(UD)                        # leaves out
if tmm2.colsb % 4:                   # whole dwords
    fault(UD)
if cr0 >> 3 & 1 or xfd >> 18 & 1:    # CR0.TS, or the OS keeps the
    fault(NM)                        # tiles from this thread
# ACE's exception class for these forms asks for XCR0 bit 20
# (SCALEDATA) too
r = src3 & 15                        # bits 3:0 of imm8 or r32
x = tmm2.row[r]
n = tmm2.colsb // 4 if r < tmm2.rows else 0
for i in range(16):
    if i < n:
        v = to_bf16_ne(x.f32[i])
        zmm1.d[i] = v                # the high half 0
    else:                            # past the tile's rows or colsb
        zmm1.d[i] = 0
start_row = 0

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

TCVTROWPS2BF16L zmm, tmm, r32 64-bit mode only

AMX-E8-EVEX

TCVTROWPS2BF16L zmm, tmm, imm8 64-bit mode only

AMX-E7-EVEX

Attributes

What else XED records about the forms. How to read.

All forms

may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to TCVTROWPS2BF16L, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AMX-AVX512 instructions

• TCVTROWD2PS
• TCVTROWPS2BF16H
• TCVTROWPS2PHH
• TCVTROWPS2PHL
• TILEMOVROW

More ACE instructions

• BSRINIT
• BSRMOVF
• BSRMOVH
• BSRMOVL
• LDTILECFG
• STTILECFG
• TCVTROWD2PS
• TCVTROWPS2BF16H
• TCVTROWPS2PHH
• TCVTROWPS2PHL
• TILEMOVCOL
• TILEMOVROW
• TILERELEASE
• TILEZERO
• TOP2BF16PS
• TOP4BSSD
• TOP4BSUD
• TOP4BUSD
• TOP4BUUD
• TOP4MXBF8PS
• TOP4MXBHF8PS
• TOP4MXBSSPS
• TOP4MXHBF8PS
• TOP4MXHF8PS