x86-64.net

Instruction

TCVTROWPS2PHH

Moves one row of a tile to a ZMM register, converting single precision to half precision in the high half of each dword and zeroing the low half.

Extensions
Forms
2 (2 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of TCVTROWPS2PHH that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
TCVTROWPS2PHH zmm, tmm, r32 64-bit mode only TCVTROWPS2PHH_ZMMf16_TMMf32_GPR32u32EVEX.512.NP.0F38.W0 6D /rACE v1 or AMX_AVX512
TCVTROWPS2PHH zmm, tmm, imm8 64-bit mode only TCVTROWPS2PHH_ZMMf16_TMMf32_IMM8EVEX.512.NP.0F3A.W0 07 /r ibACE v1 or AMX_AVX512

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to TCVTROWPS2PHH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_tile_cvtrowps2phh __m512h _tile_cvtrowps2phh(const int tsrc, const int row)

TCVTROWPS2PHH zmm, tmm, r32 EVEX.512 -mamx-avx512 -mavx10.2

_tile_cvtrowps2phhi __m512h _tile_cvtrowps2phhi(const int tsrc, const int imm8)

TCVTROWPS2PHH zmm, tmm, imm8 EVEX.512 -mamx-avx512 -mavx10.2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AMX_AVX512

ACE v1
CPUID.(EAX=07H,ECX=1):ECX[11] ACE
CPUID.(EAX=1DH,ECX=2):EAX[7:0] ≥ 1 ACE version

or

AMX_AVX512
CPUID.(EAX=1EH,ECX=1):EAX[7] AMX_AVX512

Diamond Rapids

More AMX-AVX512 instructions

More ACE instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026)
  4. x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.