TCVTROWPS2PHH

TCVTROWPS2PHH moves one row of singles from a tile into a ZMM register as TILEMOVROW does and rounds each to FP16, IEEE half precision, in the high half of its dword; the low half is zero. TCVTROWPS2PHL uses the low half. A row past the tile’s rows gives a zero register, and elements past the row’s width are zero dwords.

An FP16 conversion, with its own rules#

Rounding is always to nearest even, and MXCSR is neither read nor written. Unlike bfloat16 in TCVTROWPS2BF16H, FP16 has a narrower exponent than a single, so the range matters. 65520 lies halfway between the largest FP16 number, 65504, and 65536, and the tie goes to +infinity (7C00H). At the small end, FP16 denormals are real results: 2^-24 gives 0001H, and 2^-25, a tie with zero, gives 0. A denormal single becomes a zero, as the ISE states, and rounding would give that anyway, so far below the FP16 range. And 1 + 2^-11 and 1 + 3 × 2^-11 are ties that give the even 3C00H and 3C02H.

VCVTPS2PH rounds the same numbers but as MXCSR.RC or its immediate says, and it can report exceptions; here nothing is raised or flagged, and there is no embedded rounding. The ISE adds that MXCSR.FTZ covers only FP32 and FP64 results, so it does not stop these denormals.

Pairs for TDPFP16PS#

A bitwise OR of TCVTROWPS2PHL on one row with TCVTROWPS2PHH on the next gives a register of FP16 pairs, the interleaved form that TDPFP16PS wants in its B, written to memory for a later TILELOADD.

In our builds#

GCC 14 has no -mamx-avx512 option. With it and -mavx512fp16, Clang 23 at -O2 compiles _tile_cvtrowps2phh(2, r) to tcvtrowps2phh zmm0, tmm2, edi; _tile_cvtrowps2phhi(2, 1) gives the immediate form, 62 F3 7C 48 07 CA 01 for ZMM1 and TMM2, and the return type is __m512h. An OR of the immediate L and H intrinsics on rows 0 and 1 gave TCVTROWPS2PHL, TCVTROWPS2PHH and VORPS. Zen 5 has no AMX, and this site’s recorded cases include none of TCVTROWPS2PHH.

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

on = xcr0 if cr4 >> 18 & 1 else 0    # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 3 != 3:                # TILECFG and TILEDATA
    fault(UD)
if on & 0xE6 != 0xE6:                # AVX-512's state, AVX's and
    fault(UD)                        # SSE's
if palette == 0 or not tmm2.rows:    # no configuration, or a tile it
    fault(UD)                        # leaves out
if tmm2.colsb % 4:                   # whole dwords
    fault(UD)
if cr0 >> 3 & 1 or xfd >> 18 & 1:    # CR0.TS, or the OS keeps the
    fault(NM)                        # tiles from this thread
# ACE's exception class for these forms asks for XCR0 bit 20
# (SCALEDATA) too
r = src3 & 15                        # bits 3:0 of imm8 or r32
x = tmm2.row[r]
n = tmm2.colsb // 4 if r < tmm2.rows else 0
for i in range(16):
    if i < n:
        v = to_f16_ne(x.f32[i])
        zmm1.d[i] = v << 16          # the low half 0
    else:                            # past the tile's rows or colsb
        zmm1.d[i] = 0
start_row = 0

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

TCVTROWPS2PHH zmm, tmm, r32 64-bit mode only

AMX-E8-EVEX

TCVTROWPS2PHH zmm, tmm, imm8 64-bit mode only

AMX-E7-EVEX

Attributes

What else XED records about the forms. How to read.

All forms

may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to TCVTROWPS2PHH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AMX-AVX512 instructions

• TCVTROWD2PS
• TCVTROWPS2BF16H
• TCVTROWPS2BF16L
• TCVTROWPS2PHL
• TILEMOVROW

More ACE instructions

• BSRINIT
• BSRMOVF
• BSRMOVH
• BSRMOVL
• LDTILECFG
• STTILECFG
• TCVTROWD2PS
• TCVTROWPS2BF16H
• TCVTROWPS2BF16L
• TCVTROWPS2PHL
• TILEMOVCOL
• TILEMOVROW
• TILERELEASE
• TILEZERO
• TOP2BF16PS
• TOP4BSSD
• TOP4BSUD
• TOP4BUSD
• TOP4BUUD
• TOP4MXBF8PS
• TOP4MXBHF8PS
• TOP4MXBSSPS
• TOP4MXHBF8PS
• TOP4MXHF8PS