TCVTROWPS2PHL

TCVTROWPS2PHL moves one row of singles from a tile into a ZMM register and rounds each to FP16, IEEE half precision, as TCVTROWPS2PHH does, but puts the result in the low half of its dword and zeros the high half. That page covers the rounding to nearest even, the ties, the FP16 denormals that come out and the single denormals that become zero; TILEMOVROW’s covers the row number, its zeros for a row that is not there, and the faults.

Low half, so an FP16 array after narrowing#

Every result is the H form’s shifted down by 16 bits, so 1.0 gives 00003C00H. The lower 16 bits of each dword are also where the even element of an FP16 pair lies, which makes this form the partner for the lower row when two rows are merged for TDPFP16PS.

With the upper half zero, VPMOVDW can then narrow the 16 dwords to 16 words in a YMM register, an array of FP16 numbers like the one VCVTPS2PHX makes straight from a ZMM register of singles; that instruction, though, follows MXCSR and an EVEX rounding override and flags exceptions.

Prefixes that change meaning#

The register form is EVEX opcode 6Dh of map 0F38 with the 66 prefix bits, next to TCVTROWPS2PHH’s no prefix. The immediate form is opcode 77h of map 0F3A with the F2 prefix bits, as in tcvtrowps2phl zmm1, tmm2, 1, 62 F3 7F 48 77 CA 01. The same prefix on opcode 07h is TCVTROWPS2BF16H, so a prefix does not name a type across these two opcodes.

In our builds#

GCC 14 has no -mamx-avx512 option. With it and -mavx512fp16, Clang 23 at -O2 compiles _tile_cvtrowps2phl(2, 1) with a constant row through a register, mov eax, 1 and tcvtrowps2phl zmm0, tmm2, eax; _tile_cvtrowps2phli(2, 1) gives the immediate form. Zen 5 has no AMX, and this site’s recorded cases include none of TCVTROWPS2PHL.

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

on = xcr0 if cr4 >> 18 & 1 else 0    # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 3 != 3:                # TILECFG and TILEDATA
    fault(UD)
if on & 0xE6 != 0xE6:                # AVX-512's state, AVX's and
    fault(UD)                        # SSE's
if palette == 0 or not tmm2.rows:    # no configuration, or a tile it
    fault(UD)                        # leaves out
if tmm2.colsb % 4:                   # whole dwords
    fault(UD)
if cr0 >> 3 & 1 or xfd >> 18 & 1:    # CR0.TS, or the OS keeps the
    fault(NM)                        # tiles from this thread
# ACE's exception class for these forms asks for XCR0 bit 20
# (SCALEDATA) too
r = src3 & 15                        # bits 3:0 of imm8 or r32
x = tmm2.row[r]
n = tmm2.colsb // 4 if r < tmm2.rows else 0
for i in range(16):
    if i < n:
        v = to_f16_ne(x.f32[i])
        zmm1.d[i] = v                # the high half 0
    else:                            # past the tile's rows or colsb
        zmm1.d[i] = 0
start_row = 0

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

TCVTROWPS2PHL zmm, tmm, r32 64-bit mode only

AMX-E8-EVEX

TCVTROWPS2PHL zmm, tmm, imm8 64-bit mode only

AMX-E7-EVEX

Attributes

What else XED records about the forms. How to read.

All forms

may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to TCVTROWPS2PHL, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AMX-AVX512 instructions

• TCVTROWD2PS
• TCVTROWPS2BF16H
• TCVTROWPS2BF16L
• TCVTROWPS2PHH
• TILEMOVROW

More ACE instructions

• BSRINIT
• BSRMOVF
• BSRMOVH
• BSRMOVL
• LDTILECFG
• STTILECFG
• TCVTROWD2PS
• TCVTROWPS2BF16H
• TCVTROWPS2BF16L
• TCVTROWPS2PHH
• TILEMOVCOL
• TILEMOVROW
• TILERELEASE
• TILEZERO
• TOP2BF16PS
• TOP4BSSD
• TOP4BSUD
• TOP4BUSD
• TOP4BUUD
• TOP4MXBF8PS
• TOP4MXBHF8PS
• TOP4MXBSSPS
• TOP4MXHBF8PS
• TOP4MXHF8PS