Instruction
TDCALL
Calls the SEAM module from a trust domain, a guest in SEAM non-root operation, by a VM exit.
- Extensions
- Forms
- 1 (1 Legacy)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
TDCALL
TDCALL | 66 0F 01 CC | Base instruction set |
Latency and throughput
| Model | TDCALL |
|---|---|
| Sapphire Rapids | 100 / 0.25p0156 |
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
if not vmx_nonroot:
fault(UD) # outside a TD or another guest
if CPL > 0:
fault(GP, 0)
vm_exit(77, 0) # to the TDX module, or to the
# hypervisor of another guest
Not run on a processor: the probe never runs TDCALL, a trust domain's call to the TDX module.
Operands
| Operand | Kind | Action |
|---|---|---|
TDCALL | ||
RCX | implicit | read |
Flags
None: XED records no flag that the forms test or change.
Attributes
What else XED records about the forms. How to read.
- All forms
- privileged: CPL 0 only; may abort a TSX transaction
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
TDX | No CPUID bit: processors with SEAM report its range register (SEAMRR) in bit 15 of the IA32_MTRRCAP MSR, and the TDX module has to be loaded. | Emerald Rapids, Granite Rapids, Diamond Rapids |
More TDX instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - LLVM 23.1.2's x86 scheduling models (commit
85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3 (325384-093, September 2026): Volume 3C, page 35-9 (TDCALL)
- Linux kernel documentation: Intel Trust Domain Extensions (TDX)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The timings come from LLVM's scheduling models, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.