Instruction
TDPBF8PS
Multiplies two tiles of E5M2 FP8 values and accumulates each row-by-column dot product into a single-precision tile.
- Extensions
- Forms
- 1 (1 VEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
TDPBF8PS tmm, tmm, tmm 64-bit mode only
TDPBF8PS_TMMf32_TMM4bf8_TMM4bf8 | VEX.LZ.NP.MAP5.W0 FD /r | AMX_FP8 |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to TDPBF8PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_tile_dpbf8ps
void _tile_dpbf8ps(const int dst, const int src1, const int src2) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AMX_FP8 | AMX_FP8 | Diamond Rapids |
More AMX-FP8 instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.