TDPBSSD

TDPBSSD is the signed-byte matrix multiply of AMX: C += A × B on three tiles. Each dword of A and B holds four signed bytes, so A is M rows of K dwords, B is K rows of N dwords, and C is M rows of N 32-bit sums. Element C[m][n] gains the dot product of row m of A with column n of B, taken four bytes at a time. With full tiles of 16 rows of 64 bytes, one instruction makes 16 × 16 sums of 64 products each. B must therefore hold four consecutive rows of its matrix packed into each dword, as the AMX-INT8 page shows. The other sign combinations are TDPBSUD, TDPBUSD and TDPBUUD, the letter after TDPB giving A’s type; VPDPBSSD does the same arithmetic in a vector register.

Shapes, checked#

The dimensions come from the tile configuration that LDTILECFG loaded, and the instruction raises #UD rather than compute when they do not fit: the three tiles must be different registers, C and A must have as many rows, A’s dwords per row must equal B’s rows, B and C must have rows of the same width, in whole dwords, and no tile may be one the configuration leaves out. Without a configuration it raises #UD too. It raises #NM while bit 18 of the IA32_XFD MSR is set, which lets an operating system give the 8 KiB of tile data only to the threads that use it (AMX tiles in the ABIs).

Sums that wrap#

Each sum is a 32-bit integer that wraps on overflow; AMX has no saturating form. A product is at most 16384 (-128 × -128), so a full tile adds at most 2^20 to an element: from zero, an accumulator takes 2047 such instructions without any risk of overflow.

In compiled code#

With -mamx-int8, GCC 14 and Clang 23 at -O2 compile _tile_dpbssd(0, 1, 2), whose arguments are constant tile numbers, to tdpbssd tmm0, tmm1, tmm2; the program builds the 64-byte configuration itself and loads it with _tile_loadconfig. Clang 23 also has a tile type, __tile1024i, that carries its shape: given three of them and __tile_dpbssd(&c, a, b) in a loop, it chose the registers, wrote the configuration on the stack, ran LDTILECFG before the loop and TILERELEASE before returning. GCC 14 has no such type.

In the optimization guide

What the optimization guide says about TDPBSSD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Golden Cove and Raptor Cove

• Vectors, AVX-512 and AMX: On Sapphire and Emerald Rapids, a tile multiplication (tdp*) can start every 16 cycles and takes 52; a tile load every 8, taking 45; and loading the tile configuration takes about 204 cycles, worth doing once rather than in every call.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

on = xcr0 if cr4 >> 18 & 1 else 0    # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 3 != 3:                # TILECFG and TILEDATA
    fault(UD)
if palette != 1:                     # 0: no tiles configured; ACE's
    fault(UD)                        # palette 2 multiplies no tiles
t = tmm1.number                      # three different tiles
if t == tmm2.number or t == tmm3.number:
    fault(UD)
if tmm2.number == tmm3.number:
    fault(UD)
if 0 in (tmm1.rows, tmm2.rows, tmm3.rows):
    fault(UD)                        # one TILECFG leaves out
if tmm1.colsb % 4 or tmm2.colsb % 4:
    fault(UD)                        # rows of whole dwords
if tmm2.rows != tmm1.rows:           # A: M rows, as C
    fault(UD)
if tmm2.colsb // 4 != tmm3.rows:     # A: K dwords, B: K rows
    fault(UD)
if tmm3.colsb != tmm1.colsb:         # B: N dwords, as C
    fault(UD)
# K and N within the TMUL unit's 16 and 64 bytes (CPUID leaf
# 1EH): true of every tile of palette 1
if xfd >> 18 & 1:                    # the OS keeps the tiles from
    fault(NM)                        # this thread
for m in range(tmm1.rows):
    x = tmm2.row[m]                  # row m of A
    for n in range(tmm1.colsb // 4):
        s = tmm1.row[m].d[n]
        for k in range(tmm2.colsb // 4):
            y = tmm3.row[k]          # row k of B
            for j in range(4):
                a = x.sb[4 * k + j]
                s += a * y.sb[4 * n + j]
        tmm1.row[m].d[n] = s         # modulo 2^32
start_row = 0
# tmm1 is zeroed past its rows and colsb

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AMX-E4

Attributes

What else XED records about the forms. How to read.

All forms

may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to TDPBSSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AMX-INT8 instructions

• TDPBSUD
• TDPBUSD
• TDPBUUD