TDPBSUD

TDPBSUD is the AMX matrix multiply for signed bytes in A and unsigned bytes in B: C += A × B on three tiles, each dword of A and B holding four bytes and each element of C a 32-bit sum that wraps on overflow. It is one of four sign combinations that differ only in the prefix bits of the VEX encoding, F3 for this one, and TDPBSSD’s page covers what they share: the shapes the tile configuration must give, the #UD when they do not fit, the #NM that lets an operating system hand out the tile state on demand, and how compilers handle tiles. Its vector relative is VPDPBSUD of AVX-VNNI-INT8, with the same signedness in the same order.

The mirror of TDPBUSD#

TDPBUSD takes the unsigned bytes from A and the signed ones from B; TDPBSUD swaps the roles. Each product lies between -32,640 (-128 times 255) and 32,385 (127 times 255), the same range, so a full tile again adds at most 2,088,960 in magnitude to an element per instruction, and an accumulator that starts at zero takes 1,028 of them before a sum could wrap. The choice between the two follows the data: whichever matrix holds the unsigned values, such as values clamped at zero, goes in the operand that reads them as unsigned. Since B is stored with groups of four rows interleaved in each dword, as the AMX-INT8 page shows, swapping A and B also means repacking both.

In our builds#

With -mamx-int8, GCC 14 and Clang 23 at -O2 compile _tile_dpbsud(0, 1, 2), whose arguments are tile numbers, to tdpbsud tmm0, tmm1, tmm2, the bytes C4 E2 6A 5E C1. Like every AMX instruction it runs only in 64-bit mode, and inside a TSX transaction it aborts the transaction. Zen 5 has no AMX, and this site’s recorded cases include none of TDPBSUD.

In the optimization guide

What the optimization guide says about TDPBSUD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Golden Cove and Raptor Cove

• Vectors, AVX-512 and AMX: On Sapphire and Emerald Rapids, a tile multiplication (tdp*) can start every 16 cycles and takes 52; a tile load every 8, taking 45; and loading the tile configuration takes about 204 cycles, worth doing once rather than in every call.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

on = xcr0 if cr4 >> 18 & 1 else 0    # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 3 != 3:                # TILECFG and TILEDATA
    fault(UD)
if palette != 1:                     # 0: no tiles configured; ACE's
    fault(UD)                        # palette 2 multiplies no tiles
t = tmm1.number                      # three different tiles
if t == tmm2.number or t == tmm3.number:
    fault(UD)
if tmm2.number == tmm3.number:
    fault(UD)
if 0 in (tmm1.rows, tmm2.rows, tmm3.rows):
    fault(UD)                        # one TILECFG leaves out
if tmm1.colsb % 4 or tmm2.colsb % 4:
    fault(UD)                        # rows of whole dwords
if tmm2.rows != tmm1.rows:           # A: M rows, as C
    fault(UD)
if tmm2.colsb // 4 != tmm3.rows:     # A: K dwords, B: K rows
    fault(UD)
if tmm3.colsb != tmm1.colsb:         # B: N dwords, as C
    fault(UD)
# K and N within the TMUL unit's 16 and 64 bytes (CPUID leaf
# 1EH): true of every tile of palette 1
if xfd >> 18 & 1:                    # the OS keeps the tiles from
    fault(NM)                        # this thread
for m in range(tmm1.rows):
    x = tmm2.row[m]                  # row m of A
    for n in range(tmm1.colsb // 4):
        s = tmm1.row[m].d[n]
        for k in range(tmm2.colsb // 4):
            y = tmm3.row[k]          # row k of B
            for j in range(4):
                a = x.sb[4 * k + j]
                s += a * y.b[4 * n + j]
        tmm1.row[m].d[n] = s         # modulo 2^32
start_row = 0
# tmm1 is zeroed past its rows and colsb

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AMX-E4

Attributes

What else XED records about the forms. How to read.

All forms

may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to TDPBSUD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AMX-INT8 instructions

• TDPBSSD
• TDPBUSD
• TDPBUUD