TDPBUSD

TDPBUSD is the AMX matrix multiply for unsigned bytes in A and signed bytes in B: C += A × B on three tiles, each dword of A and B holding four bytes and each element of C a 32-bit sum. It is the tile form of the arithmetic of VPDPBUSD, with the same signedness in the same order, and one of four sign combinations that differ only in the prefix: none for TDPBUUD, 66 for TDPBUSD, F3 for TDPBSUD and F2 for TDPBSSD. TDPBSSD’s page covers what they share: the shapes the tile configuration must give, the #UD when they do not fit, the #NM that lets an operating system hand out tile state on demand, and how compilers handle tiles.

The range of a sum#

A product of an unsigned and a signed byte lies between -32,640 (255 times -128) and 32,385 (255 times 127), and a full tile adds 64 of them to each element, at most 2,088,960 in magnitude per instruction. From zero, an accumulator therefore takes 1,028 such instructions before a sum could wrap, half as many as TDPBSSD’s.

Where it appears#

Intel’s optimization manual builds its int8 examples on TDPBUSD. In the convolution of Example 20-21 (Section 20.11.1), each block of TDPBUSD results is converted to singles, scaled and offset with VFMADD213PS, clamped at zero with VPMAXSD and packed into unsigned bytes with VPMOVUSDB, the type that TDPBUSD reads from A.

In compiled code#

With -mamx-int8, GCC 14 and Clang 23 at -O2 compile _tile_dpbusd(0, 1, 2), whose arguments are tile numbers, to tdpbusd tmm0, tmm1, tmm2. AMX instructions exist only in 64-bit mode, and an attempt to run TDPBUSD inside a TSX transaction aborts it. Zen 5 has no AMX, and this site’s recorded cases include none of TDPBUSD.

In the optimization guide

What the optimization guide says about TDPBUSD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Golden Cove and Raptor Cove

• Vectors, AVX-512 and AMX: On Sapphire and Emerald Rapids, a tile multiplication (tdp*) can start every 16 cycles and takes 52; a tile load every 8, taking 45; and loading the tile configuration takes about 204 cycles, worth doing once rather than in every call.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

on = xcr0 if cr4 >> 18 & 1 else 0    # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 3 != 3:                # TILECFG and TILEDATA
    fault(UD)
if palette != 1:                     # 0: no tiles configured; ACE's
    fault(UD)                        # palette 2 multiplies no tiles
t = tmm1.number                      # three different tiles
if t == tmm2.number or t == tmm3.number:
    fault(UD)
if tmm2.number == tmm3.number:
    fault(UD)
if 0 in (tmm1.rows, tmm2.rows, tmm3.rows):
    fault(UD)                        # one TILECFG leaves out
if tmm1.colsb % 4 or tmm2.colsb % 4:
    fault(UD)                        # rows of whole dwords
if tmm2.rows != tmm1.rows:           # A: M rows, as C
    fault(UD)
if tmm2.colsb // 4 != tmm3.rows:     # A: K dwords, B: K rows
    fault(UD)
if tmm3.colsb != tmm1.colsb:         # B: N dwords, as C
    fault(UD)
# K and N within the TMUL unit's 16 and 64 bytes (CPUID leaf
# 1EH): true of every tile of palette 1
if xfd >> 18 & 1:                    # the OS keeps the tiles from
    fault(NM)                        # this thread
for m in range(tmm1.rows):
    x = tmm2.row[m]                  # row m of A
    for n in range(tmm1.colsb // 4):
        s = tmm1.row[m].d[n]
        for k in range(tmm2.colsb // 4):
            y = tmm3.row[k]          # row k of B
            for j in range(4):
                a = x.b[4 * k + j]
                s += a * y.sb[4 * n + j]
        tmm1.row[m].d[n] = s         # modulo 2^32
start_row = 0
# tmm1 is zeroed past its rows and colsb

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AMX-E4

Attributes

What else XED records about the forms. How to read.

All forms

may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to TDPBUSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AMX-INT8 instructions

• TDPBSSD
• TDPBSUD
• TDPBUUD