TDPFP16PS

TDPFP16PS is the half-precision matrix multiply of AMX: C += A × B with a pair of IEEE FP16 values in each dword of A and B, and singles in C. It came with AMX-FP16, which Intel’s manual lists on the Granite Rapids Xeon 6 P-core processors, and is otherwise TDPBF16PS with another input format: the same shapes and faults, the same two partial sums per element, of the low and the high halves of the pairs, each product added with one rounding, the two sums then added to each other and the total to C, always rounding to nearest even, without MXCSR and without exceptions.

Where FP16 differs from bfloat16#

The two 16-bit formats split their bits differently. Bfloat16 keeps the 8-bit exponent of a single and only 7 fraction bits; FP16 has a 5-bit exponent and 10 fraction bits, so it is three bits more precise but reaches only 65504, and its smallest normal number is 2^-14. Every FP16 value, and every product of two, fits a single exactly, so the rounding happens only as the products are summed.

The denormals are treated differently too. TDPBF16PS takes denormal inputs as zero, but TDPFP16PS keeps FP16 denormals as the numbers they are, down to 2^-24, which matters with a range this small. Only on the single-precision side are denormals flushed: a denormal sum becomes zero, as with bfloat16.

Using it#

With -mamx-fp16, GCC 14 and Clang 23 at -O2 compile _tile_dpfp16ps(0, 1, 2) to tdpfp16ps tmm0, tmm1, tmm2. Clang 23’s __tile1024i type also has __tile_dpfp16ps. The data comes in as FP16 pairs, which AVX-512 FP16 code or VCVTPS2PH can produce; B, as in every AMX multiply, holds two consecutive rows of its matrix interleaved in each dword. The instruction was first specified in Intel’s ISE and has since moved to the SDM. Its vector relative is VDPPHPS, the AVX10.2 dot product of FP16 pairs into singles.

In the optimization guide

What the optimization guide says about TDPFP16PS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Redwood Cove

• Execution, vectors and AMX: On Granite Rapids, AMX also multiplies tiles of half-precision values, with TDPFP16PS; Intel’s manual gives its rates only for the older tile operations.

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

on = xcr0 if cr4 >> 18 & 1 else 0    # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 3 != 3:                # TILECFG and TILEDATA
    fault(UD)
if palette != 1:                     # 0: no tiles configured; ACE's
    fault(UD)                        # palette 2 multiplies no tiles
t = tmm1.number                      # three different tiles
if t == tmm2.number or t == tmm3.number:
    fault(UD)
if tmm2.number == tmm3.number:
    fault(UD)
if 0 in (tmm1.rows, tmm2.rows, tmm3.rows):
    fault(UD)                        # one TILECFG leaves out
if tmm1.colsb % 4 or tmm2.colsb % 4:
    fault(UD)                        # rows of whole dwords
if tmm2.rows != tmm1.rows:           # A: M rows, as C
    fault(UD)
if tmm2.colsb // 4 != tmm3.rows:     # A: K dwords, B: K rows
    fault(UD)
if tmm3.colsb != tmm1.colsb:         # B: N dwords, as C
    fault(UD)
# K and N within the TMUL unit's 16 and 64 bytes (CPUID leaf
# 1EH): true of every tile of palette 1
if xfd >> 18 & 1:                    # the OS keeps the tiles from
    fault(NM)                        # this thread
for m in range(tmm1.rows):
    x = tmm2.row[m]                  # row m of A
    for n in range(tmm1.colsb // 4):
        e = o = cvt_f32_ne(0)        # two sums, from +0
        for k in range(tmm2.colsb // 4):
            y = tmm3.row[k]          # row k of B
            a = x.f16[2 * k]
            b = y.f16[2 * n]
            e = fmadd_ne(a, b, e)
            a = x.f16[2 * k + 1]
            b = y.f16[2 * n + 1]
            o = fmadd_ne(a, b, o)
        c = tmm1.row[m].f32[n]
        r = add_ne(e, o)
        tmm1.row[m].f32[n] = add_ne(c, r)
start_row = 0
# tmm1 is zeroed past its rows and colsb

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AMX-E4

Attributes

What else XED records about the forms. How to read.

All forms

may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to TDPFP16PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.