TDPHBF8PS

TDPHBF8PS is TDPBHF8PS with the formats the other way round: C += A × B with A in E4M3 and B in E5M2, four values per dword, singles in C. The first letter after TDP gives the first source’s format, H for HF8 (E4M3), and the second letter the second source’s, B for BF8 (E5M2). The range of the products is the same, since multiplication commutes, and TDPBF8PS covers the shapes, the faults and the exact sum rounded once.

Why both orders exist#

The two sources are not interchangeable even with the formats swapped along. A × B and B × A are different matrix products: A supplies whole rows of C and B whole columns, and B is the tile with several rows of its matrix packed into each dword. So a program with an E5M2 matrix on the left of the product uses TDPBHF8PS, and one with it on the right uses this instruction. Here it is B that can hold infinities and more NaN codes, while A’s only NaNs are 7FH and FFH.

For an example, take E4M3 1 (38H) and 2^-8 (02H, a denormal) in the first dword of A and 2^-8 in its second, against E5M2 1 (3CH) and 2^-16 (01H) in row 0 of B and 2^-16 in row 1: the sum is exactly 1 + 2^-23, and with C = 1 the second rounding gives 2 (40000000H), as in TDPBF8PS’s example. A sum in which +infinity (7CH) and -infinity (FCH) of B meet gives the QNaN indefinite FFC00000H.

In our builds#

GCC 14 has no -mamx-fp8 option. With it, Clang 23 at -O2 compiles _tile_dphbf8ps(0, 1, 2) to tdphbf8ps tmm0, tmm1, tmm2, the bytes C4 E5 6A FD C1: opcode FDh of VEX map 5 with the F3 prefix bits. Zen 5 has no AMX, and this site’s recorded cases include none of TDPHBF8PS.

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

on = xcr0 if cr4 >> 18 & 1 else 0    # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 3 != 3:                # TILECFG and TILEDATA
    fault(UD)
if palette != 1:                     # 0: no tiles configured; ACE's
    fault(UD)                        # palette 2 multiplies no tiles
t = tmm1.number                      # three different tiles
if t == tmm2.number or t == tmm3.number:
    fault(UD)
if tmm2.number == tmm3.number:
    fault(UD)
if 0 in (tmm1.rows, tmm2.rows, tmm3.rows):
    fault(UD)                        # one TILECFG leaves out
if tmm1.colsb % 4 or tmm2.colsb % 4:
    fault(UD)                        # rows of whole dwords
if tmm2.rows != tmm1.rows:           # A: M rows, as C
    fault(UD)
if tmm2.colsb // 4 != tmm3.rows:     # A: K dwords, B: K rows
    fault(UD)
if tmm3.colsb != tmm1.colsb:         # B: N dwords, as C
    fault(UD)
# K and N within the TMUL unit's 16 and 64 bytes (CPUID leaf
# 1EH): true of every tile of palette 1
if xfd >> 18 & 1:                    # the OS keeps the tiles from
    fault(NM)                        # this thread
for m in range(tmm1.rows):
    x = tmm2.row[m]                  # row m of A
    for n in range(tmm1.colsb // 4):
        s = 0                        # the exact sum
        for i in range(tmm2.colsb):  # byte i of A's row: byte
            y = tmm3.row[i // 4]     # i % 4 of dword i // 4
            b = y.bf8[4 * n + i % 4]
            p = mul_exact(x.hf8[i], b)
            s = add_exact(s, p)
        c = tmm1.row[m].f32[n]
        r = round_ftz(s, 0)          # rounded once
        t = add_exact(c, r)
        tmm1.row[m].f32[n] = round_ftz(t, 0)
start_row = 0
# tmm1 is zeroed past its rows and colsb

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AMX-E4

Attributes

What else XED records about the forms. How to read.

All forms

always rounds to nearest even; may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to TDPHBF8PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AMX-FP8 instructions

• TDPBF8PS
• TDPBHF8PS
• TDPHF8PS