TEST

TEST ANDs its operands, sets the flags from the result and discards it: it is to AND what CMP is to SUB. It has two everyday uses:

• Zero and sign. test rax, rax sets ZF when RAX is 0 and SF when it is negative, so JZ, JNZ, JS and JNS can follow it. Every condition code then gives the same answer as after cmp rax, 0, since both leave CF and OF clear, and TEST needs no immediate byte. GCC 14 and Clang 23 at -O2 compile both x == 0 and x < 0 to test rdi, rdi and a branch.
• Bits. test reg, mask sets ZF when none of the bits in the mask is set, so JNZ means “any of them is”. For a single bit whose number is in a register, BT copies that bit to CF instead.

APX’s CTESTscc is TEST under a condition, as CCMPscc is CMP under one.

The immediate#

TEST has no form with a sign-extended 8-bit immediate, which CMP, AND and the other arithmetic instructions have: its immediate is as wide as the operand, up to 32 bits. When the mask fits in the low byte, a byte operand is shorter, and Clang 23 compiles if (x & 8) to test dil, 8, four bytes, where test edi, 8 would take six.

Parity#

PF reflects only the low 8 bits of the result, as it does after the arithmetic and logical instructions in general, so test eax, eax followed by JP says nothing about the parity of all 32 bits. Folding the halves together with XOR first, as GCC and Clang do for __builtin_parity, or a POPCNT, gives that.

The /1 encodings#

TEST with an immediate is F6 /0 or F7 /0. XED decodes the same opcodes with /1 in ModRM.reg as TEST too, and marks those forms undocumented: AMD’s opcode map lists TEST under both /0 and /1, while Intel’s leaves /1 empty. Zen 5 ran the /1 forms recorded here exactly as the /0 ones.

In the optimization guide

What the optimization guide says about TEST, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Front end

• Macro-fusion: Intel’s cores since Sandy Bridge (Skylake) fuse test and and with any conditional branch; cmp, add and sub with branches on the equal, unsigned and signed comparisons, but not on the sign, parity or overflow flag alone; and inc and dec only with branches on equality and the signed comparisons.
• Macro-fusion: AMD’s Zen 3 to Zen 5 fuse more: cmp, test, add, sub, and, or, xor, inc and dec with any conditional branch, except that on Zen 3 and Zen 4 inc and dec do not fuse with a branch that reads the carry flag, which Intel’s cores do not fuse either (Zen 5, Zen 4, Zen 3). sources differ
• Macro-fusion: With a memory operand, Intel’s Sandy Bridge to Skylake do not fuse an instruction that also has an immediate, while AMD’s Zen 3 and Zen 4 still fuse cmp and test unless a displacement comes with the immediate or the address is relative to RIP. sources differ
• Macro-fusion: On Intel’s cores the choice of instruction decides fusion more often, so Intel prefers test to cmp for a comparison with zero, as test fuses with every condition.

Bulldozer to Excavator

• Branches: A cmp or test directly followed by a conditional branch fuses into one op, unless the compare uses a RIP-relative address or has a displacement as well as an immediate; no other instruction fuses. sources differ

Haswell and Broadwell

• Front end: CMP, ADD and SUB fuse with a following conditional jump that tests carry, zero, or a signed or unsigned comparison; INC and DEC only with one that tests zero or a signed comparison; TEST and AND with any.

Ice Lake to Rocket Lake

• Front end: A cmp, add, sub, inc or dec fuses with a following jump on zero, carry or an unsigned or signed comparison, and test or and with any conditional jump; or, xor, adc, sbb, shifts and js, jo and jp never fuse.

Sandy Bridge and Ivy Bridge

• Front end: Sandy Bridge widens macro-fusion from Nehalem’s CMP and TEST to also fuse ADD, SUB, AND, INC and DEC with a following conditional branch, fusing when the first instruction’s first operand is a register and its second operand, if any, is an immediate, a register or memory that is not RIP-relative; the pair does not fuse only when the first instruction ends on the last byte of a 64-byte line and the branch begins the next line’s first byte.

Skylake to Cooper Lake

• Front end: test and and fuse with any following conditional jump; cmp, add and sub with the jumps on equality and on the unsigned and signed comparisons, but not with js, jp or jo and their inverses; inc and dec only with those on equality and the signed comparisons.

Zen and Zen+

• Integer execution: Only a cmp or test directly followed by a conditional branch fuses into one macro-op, and not when it has a displacement together with an immediate, or an address relative to RIP; no other arithmetic or logic instruction fuses.

Zen 2

• Integer execution: Only a cmp or test followed by a conditional branch fuses into one macro-op, not one with a displacement together with an immediate or an address relative to RIP; the arithmetic and logic instructions that fuse on Zen 3 do not.

Zen 3

• Integer execution: A cmp, test, add, sub, inc, dec, and, or or xor followed by a conditional branch becomes one macro-op, also with a memory operand, unless it carries a displacement together with an immediate, addresses relative to RIP or makes the pair longer than 15 bytes; inc and dec do not fuse with a branch on the carry flag, and jrcxz never fuses.

Zen 4

• Integer execution: A cmp, test, add, sub, inc, dec, and, or or xor followed by a conditional branch becomes one macro-op, also with a memory operand, unless it carries a displacement together with an immediate, addresses relative to RIP or makes the pair longer than 15 bytes; inc and dec do not fuse with a branch on the carry flag.

Zen 5

• Integer execution: A cmp, test, add, sub, inc, dec, and, or or xor followed by a conditional branch becomes one macro-op, also with a memory operand, within limits on the sizes of its displacement and immediate.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

r = src1 & sext(src2)            # as AND, but nothing is written
of = cf = 0
sf = msb(r)
zf = r == 0
pf = parity(r)
af = UNDEFINED

Operands

Flags

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• NEG
• NOP
• NOT
• OR
• OUT
• OUTS
• PAUSE
• POP
• POPA
• POPF
• PUSH
• PUSHA
• PUSHF
• RCL
• RCR
• RET
• ROL
• ROR
• SALC
• SAR
• SBB
• SCAS
• SETcc
• SHL
• SHLD
• SHR
• SHRD
• STC
• STD
• STI
• STOS
• SUB
• UD0
• UD1
• UD2
• UDB
• XADD
• XCHG
• XLAT
• XOR

All 109 General-purpose instructions