Extensions
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

TESTUI reads the user-interrupt flag, UIF, into CF: CF = 1 means that user interrupts can be delivered, CF = 0 that they are held back, by CLUI or because the code is a user-interrupt handler, whose delivery cleared the flag. It is how a program reads UIF directly; STUI and CLUI write it. Like them, it runs at any privilege level, but unlike them it does not abort a TSX transaction.

The other flags

Intel’s manual clears ZF, OF, AF, PF and SF, so after TESTUI the flags hold UIF and nothing else. XED, from which this page takes its flags table, records only CF, as the note beside the table says; code should not rely on the other five keeping their values across a TESTUI.

In compiled code

_testui() returns UIF as an unsigned char. With -muintr, GCC 14 and Clang 23 at -O2 compile return _testui(); to xor eax, eax, TESTUI and setc al (Clang writes setb). Its main use is to save the flag before a critical section and restore it afterwards: both compilers turned

unsigned char was = _testui();
_clui();
/* ... */
if (was)
    _stui();

into TESTUI, a SETcc of CF, CLUI, the protected code and a branch around the STUI, so that a section entered with user interrupts held back leaves them held back.

Where it runs

TESTUI exists only in 64-bit mode and needs UINTR (CPUID leaf 7, EDX bit 5) and CR4.UINTR; otherwise, inside an enclave or with a LOCK prefix, it raises #UD. This site’s Zen 5 reports no UINTR, and both recorded cases raised #UD and left RFLAGS as it was, CF included.

Forms

Every encoding of TESTUI that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
TESTUI 64-bit mode only TESTUIF3 0F 01 EDUINTR

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
ModelTESTUI
Sapphire Rapids100 / 0.25p0156

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cr4 >> 25 & 1:            # CR4.UINTR; clear without UINTR
    fault(UD)
cf = uif
zf = af = of = pf = sf = 0

Run on AMD Zen 5 (EPYC 9645): 2 cases. Its cases ran where CPUID reported no UINTR, and every one raised an exception.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
TESTUI 64-bit mode only
UIFimplicitread
RFLAGSimplicitwrite

Flags

M modified; blank: not affected. How to read.
CF
All forms
M

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
UINTR

UINTR
CPUID.(EAX=07H,ECX=0):EDX[5] UINTR

Arrow Lake, Panther Lake, Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest

More UINTR instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-723 (TESTUI)
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3 (325384-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The timings come from LLVM's scheduling models, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.