TILELOADD instruction (AMX-TILE, APX)

TILELOADD fills a tile row by row from memory. Its memory operand must use a SIB byte, and the parts of the address play different roles: the base register plus displacement is the address of the first row, and the index register, shifted by the scale, is the distance between rows (the stride). Without an index register the stride is zero. Each row reads as many bytes as the tile’s configured row width, and bytes and rows beyond the configured shape are zeroed.

The load is restartable. If a fault interrupts it, the tile configuration’s start_row field records the next row, and the instruction resumes there after the fault is handled. TILELOADDT1 is the same load with a hint that the data will be reused but need not stay in the nearest caches, and TILESTORED is the matching store.

In the optimization guide

What the optimization guide says about TILELOADD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Golden Cove and Raptor Cove

Vectors, AVX-512 and AMX: On Sapphire and Emerald Rapids, a tile multiplication (tdp*) can start every 16 cycles and takes 52; a tile load every 8, taking 45; and loading the tile configuration takes about 204 cycles, worth doing once rather than in every call.
Vectors, AVX-512 and AMX: A tile load cannot take its data from stores still in the store buffer: it waits until they reach the cache.

Forms

Every encoding of TILELOADD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`TILELOADD tmm, sibmem` 64-bit mode only TILELOADD_TMMu32_MEMu32	`VEX.LZ.F2.0F38.W0 4B /r`	AMX_TILE
`TILELOADD tmm, sibmem` TILELOADD_TMMu32_MEMu32_APX	`EVEX.LLZ.F2.0F38.W0 4B /r`	APX_F + AMX_TILE

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`tmm, sibmem`
Sapphire Rapids	100 / 0.25p0156

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

on = xcr0 if cr4 >> 18 & 1 else 0    # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 3 != 3:                # TILECFG and TILEDATA
    fault(UD)
if palette != 1:                     # 0: no tiles configured; ACE's
    fault(UD)                        # palette 2 has no loads
if not tmm1.rows or tmm1.colsb % 4:  # left out, or not whole dwords
    fault(UD)
if start_row >= tmm1.rows:
    fault(UD)
if xfd >> 18 & 1:                    # the OS keeps the tiles from
    fault(NM)                        # this thread
a = mem.address                      # row 0: base + displacement
s = mem.stride                       # index * scale, 0 without one
n = tmm1.colsb
for r in range(start_row, tmm1.rows):
    tmm1.row[r] = load(a + r * s, 8 * n)
start_row = 0
# a fault in row r leaves the rows before it loaded and start_row
# = r, where the instruction goes on when it runs again
# tmm1 is zeroed past its rows, and the rows loaded past colsb

Not run on a processor: none of these processors has AMX.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`TILELOADD tmm, sibmem` 64-bit mode only
`tmm`	explicit	write
`sibmem`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms: AMX-E3
EVEX forms: AMX-E3-EVEX

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to TILELOADD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_tile_loadd` `void _tile_loadd(const int dst, const void *base, __SIZE_TYPE__ stride)`	`TILELOADD tmm, sibmem` VEX.LZ -mamx-tile

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AMX_TILE` AMX-TILE	AMX_TILE `CPUID.(EAX=07H,ECX=0):EDX[24]` AMX_TILE	Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`APX_F_AMX` APX	APX_F + AMX_TILE `CPUID.(EAX=07H,ECX=1):EDX[21]` APX_F `CPUID.(EAX=07H,ECX=0):EDX[24]` AMX_TILE	Diamond Rapids

More AMX-TILE instructions

More APX instructions

All 88 APX instructions