x86-64.net

Instruction

TILELOADD

Loads a tile from memory, row by row, with the row stride taken from the index register of its SIB-encoded address.

Extensions
Forms
2 (1 VEX, 1 EVEX)
Data
Intel XED v2026.08.23

TILELOADD fills a tile row by row from memory. Its memory operand must use a SIB byte, and the parts of the address play different roles: the base register plus displacement is the address of the first row, and the index register, shifted by the scale, is the distance between rows (the stride). Without an index register the stride is zero. Each row reads as many bytes as the tile’s configured row width, and bytes and rows beyond the configured shape are zeroed.

The load is restartable. If a fault interrupts it, the tile configuration’s start_row field records the next row, and the instruction resumes there after the fault is handled. TILELOADDT1 is the same load with a hint that the data will be reused but need not stay in the nearest caches, and TILESTORED is the matching store.

Forms

Every encoding of TILELOADD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
TILELOADD tmm, sibmem 64-bit mode only TILELOADD_TMMu32_MEMu32VEX.LZ.F2.0F38.W0 4B /rAMX_TILE
TILELOADD tmm, sibmem TILELOADD_TMMu32_MEMu32_APXEVEX.LLZ.F2.0F38.W0 4B /rAPX_F + AMX_TILE

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to TILELOADD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_tile_loadd void _tile_loadd(const int dst, const void *base, __SIZE_TYPE__ stride)

TILELOADD tmm, sibmem VEX.LZ -mamx-tile

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AMX_TILE

AMX_TILE
CPUID.(EAX=07H,ECX=0):EDX[24] AMX_TILE

Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
APX_F_AMX

APX_F + AMX_TILE
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=07H,ECX=0):EDX[24] AMX_TILE

Diamond Rapids

More AMX-TILE instructions

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  4. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.