TILELOADDRS instruction (AMX-MOVRS, APX)

TILELOADDRS loads a tile from memory as TILELOADD does and adds the read-shared hint of MOVRS: this data will probably be read by another processor before anyone writes it. The tile ends up the same; the hint only lets the processor arrange its caches, the shared levels above all, for several readers. TILELOADD’s page covers what they share: the SIB operand whose base and displacement give the first row and whose scaled index gives the stride, the zeros beyond the configured shape, and the restart from start_row after a fault.

When the hint fits

The fitting data is what many threads read and nobody changes for a long time, such as the weights of a neural network multiplied by several cores at once, the example on AMX-MOVRS. If a write does come first, it works as usual but may run slower than after a plain load, so the hint does not suit data that one processor will write next. The ISE names no latency and no specific cache behaviour.

Encoding and faults

The VEX form is opcode 4Ah of map 0F38 with the F2 prefix bits, where TILELOADD has 4Bh; TILELOADDRST1 takes the 66 prefix bits. The checks are the class AMX-E3: tile state in XCR0, a loaded configuration under palette 1, a tile the configuration gives rows of whole dwords, a SIB byte, start_row below the tile’s rows, #NM while bit 18 of IA32_XFD is set, and the memory faults; the operand needs no alignment. The APX specification adds an EVEX form (class AMX-E3-EVEX), so that the base and index can be R16 to R31. Inside a TSX transaction it aborts the transaction.

In our builds

GCC 14 has no -mamx-movrs option. With it, Clang 23 at -O2 compiles _tile_loaddrs(1, p, s) to tileloaddrs tmm1, [rdi+rsi], the bytes C4 E2 7B 4A 0C 37, and a constant stride of 64 goes through a register first, mov eax, 64, as for TILELOADD. Clang’s __tile_loaddrs fills a __tile1024i. Zen 5 has no AMX, and this site’s recorded cases include none of TILELOADDRS.

Forms

Every encoding of TILELOADDRS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`TILELOADDRS tmm, sibmem` 64-bit mode only TILELOADDRS_TMMu32_MEMu32	`VEX.LZ.F2.0F38.W0 4A /r`	AMX_MOVRS
`TILELOADDRS tmm, sibmem` TILELOADDRS_TMMu32_MEMu32_APX	`EVEX.LLZ.F2.0F38.W0 4A /r`	APX_F + AMX_MOVRS

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

on = xcr0 if cr4 >> 18 & 1 else 0    # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 3 != 3:                # TILECFG and TILEDATA
    fault(UD)
if palette != 1:                     # 0: no tiles configured; ACE's
    fault(UD)                        # palette 2 has no loads
if not tmm1.rows or tmm1.colsb % 4:  # left out, or not whole dwords
    fault(UD)
if start_row >= tmm1.rows:
    fault(UD)
if xfd >> 18 & 1:                    # the OS keeps the tiles from
    fault(NM)                        # this thread
a = mem.address                      # row 0: base + displacement
s = mem.stride                       # index * scale, 0 without one
n = tmm1.colsb
for r in range(start_row, tmm1.rows):
    tmm1.row[r] = load(a + r * s, 8 * n)
start_row = 0
# a fault in row r leaves the rows before it loaded and start_row
# = r, where the instruction goes on when it runs again
# a hint: other processors will read the data, too, before any
# of them writes it
# tmm1 is zeroed past its rows, and the rows loaded past colsb

Not run on a processor: none of these processors has AMX.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`TILELOADDRS tmm, sibmem` 64-bit mode only
`tmm`	explicit	write
`sibmem`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms: AMX-E3
EVEX forms: AMX-E3-EVEX

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to TILELOADDRS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_tile_loaddrs` `void _tile_loaddrs(const int dst, const void *base, __SIZE_TYPE__ stride)`	`TILELOADDRS tmm, sibmem` VEX.LZ -mamx-movrs

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AMX_MOVRS` AMX-MOVRS	AMX_MOVRS `CPUID.(EAX=1EH,ECX=1):EAX[8]` AMX_MOVRS	Diamond Rapids
`APX_F_AMX_MOVRS` APX	APX_F + AMX_MOVRS `CPUID.(EAX=07H,ECX=1):EDX[21]` APX_F `CPUID.(EAX=1EH,ECX=1):EAX[8]` AMX_MOVRS	Same as `AMX_MOVRS`

More AMX-MOVRS instructions

TILELOADDRST1

More APX instructions

All 88 APX instructions

When the hint fits#

Encoding and faults#

In our builds#