x86-64.net

Instruction

TILELOADDRST1

Loads a tile like TILELOADDRS, with the added hint that the data will be reused but need not stay in the nearest cache.

Extensions
Forms
2 (1 VEX, 1 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of TILELOADDRST1 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
TILELOADDRST1 tmm, sibmem 64-bit mode only TILELOADDRST1_TMMu32_MEMu32VEX.LZ.66.0F38.W0 4A /rAMX_MOVRS
TILELOADDRST1 tmm, sibmem TILELOADDRST1_TMMu32_MEMu32_APXEVEX.LLZ.66.0F38.W0 4A /rAPX_F + AMX_MOVRS

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to TILELOADDRST1, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_tile_stream_loaddrs void _tile_stream_loaddrs(const int dst, const void *base, __SIZE_TYPE__ stride)

TILELOADDRST1 tmm, sibmem VEX.LZ -mamx-movrs

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AMX_MOVRS

AMX_MOVRS
CPUID.(EAX=1EH,ECX=1):EAX[8] AMX_MOVRS

Diamond Rapids
APX_F_AMX_MOVRS

APX_F + AMX_MOVRS
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=1EH,ECX=1):EAX[8] AMX_MOVRS

Diamond Rapids

More AMX-MOVRS instructions

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026)
  4. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.