TILELOADDRST1 instruction (AMX-MOVRS, APX)

TILELOADDRST1 is TILELOADDRS in the encoding with the 66 prefix bits instead of F2: a tile load from memory with the read-shared hint, whose addressing, restart and faults that page and TILELOADD’s cover. The two relate as TILELOADDT1 and TILELOADD do, opcode 4Ah here against 4Bh there.

What the T1 adds

The ISE gives the two read-shared loads one page and one description, with the same words for both in its opcode table, and it says nothing about what the T1 changes. So the only guide is the name it shares with TILELOADDT1, which tells the processor that the data need not stay in the caches nearest the core, a meaning Intel’s optimization manual gives to that instruction and not to this one. Clang agrees in naming: the intrinsic is _tile_stream_loaddrs, as _tile_stream_loadd is TILELOADDT1’s. Taking both hints together is a reading of the names, which no document we cite states; the tile’s contents are the same in any case.

Like TILELOADDRS it has an EVEX form in the APX specification, class AMX-E3-EVEX, for base and index registers among R16 to R31.

In our builds

GCC 14 has no -mamx-movrs option. With it, Clang 23 at -O2 compiles _tile_stream_loaddrs(1, p, s) to tileloaddrst1 tmm1, [rdi+rsi], the bytes C4 E2 79 4A 0C 37, and __tile_stream_loaddrs does the same for a __tile1024i, after writing and loading a configuration. Zen 5 has no AMX, and this site’s recorded cases include none of TILELOADDRST1.

Forms

Every encoding of TILELOADDRST1 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`TILELOADDRST1 tmm, sibmem` 64-bit mode only TILELOADDRST1_TMMu32_MEMu32	`VEX.LZ.66.0F38.W0 4A /r`	AMX_MOVRS
`TILELOADDRST1 tmm, sibmem` TILELOADDRST1_TMMu32_MEMu32_APX	`EVEX.LLZ.66.0F38.W0 4A /r`	APX_F + AMX_MOVRS

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

on = xcr0 if cr4 >> 18 & 1 else 0    # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 3 != 3:                # TILECFG and TILEDATA
    fault(UD)
if palette != 1:                     # 0: no tiles configured; ACE's
    fault(UD)                        # palette 2 has no loads
if not tmm1.rows or tmm1.colsb % 4:  # left out, or not whole dwords
    fault(UD)
if start_row >= tmm1.rows:
    fault(UD)
if xfd >> 18 & 1:                    # the OS keeps the tiles from
    fault(NM)                        # this thread
a = mem.address                      # row 0: base + displacement
s = mem.stride                       # index * scale, 0 without one
n = tmm1.colsb
for r in range(start_row, tmm1.rows):
    tmm1.row[r] = load(a + r * s, 8 * n)
start_row = 0
# a fault in row r leaves the rows before it loaded and start_row
# = r, where the instruction goes on when it runs again
# both hints: read by other processors too, and need not stay in
# the nearest caches
# tmm1 is zeroed past its rows, and the rows loaded past colsb

Not run on a processor: none of these processors has AMX.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`TILELOADDRST1 tmm, sibmem` 64-bit mode only
`tmm`	explicit	write
`sibmem`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms: AMX-E3
EVEX forms: AMX-E3-EVEX

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to TILELOADDRST1, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_tile_stream_loaddrs` `void _tile_stream_loaddrs(const int dst, const void *base, __SIZE_TYPE__ stride)`	`TILELOADDRST1 tmm, sibmem` VEX.LZ -mamx-movrs

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AMX_MOVRS` AMX-MOVRS	AMX_MOVRS `CPUID.(EAX=1EH,ECX=1):EAX[8]` AMX_MOVRS	Diamond Rapids
`APX_F_AMX_MOVRS` APX	APX_F + AMX_MOVRS `CPUID.(EAX=07H,ECX=1):EDX[21]` APX_F `CPUID.(EAX=1EH,ECX=1):EAX[8]` AMX_MOVRS	Same as `AMX_MOVRS`

More AMX-MOVRS instructions

TILELOADDRS

More APX instructions

All 88 APX instructions

What the T1 adds#

In our builds#