TILELOADDT1 instruction (AMX-TILE, APX)

TILELOADDT1 loads a tile from memory exactly as TILELOADD does, and adds a hint that the data will be used again but need not be kept in the caches closest to the core. The two differ only in the prefix bits of their VEX encoding, 66 for TILELOADDT1 and F2 for TILELOADD, and TILELOADD’s page covers what they share: the SIB operand whose base and displacement give the first row and whose scaled index gives the stride, the rows and bytes zeroed beyond the configured shape, and the restart from start_row after a fault. The faults are TILELOADD’s too, including #UD without a tile configuration, and inside a TSX transaction it aborts the transaction. Intel’s APX specification adds an EVEX form, so that the base and index can be among the new registers R16 to R31.

Keeping the other matrix in L1

Intel’s optimization manual explains the use of the hint (Section 20.8). A plain tile load brings its data through L2 and L1, and in a blocked matrix multiplication the larger block of one matrix, read once, can push out of L1 the smaller block of the other that the next loop iteration reads again. Loading the block used once with TILELOADDT1 leaves L1 to the reused one. The manual’s Table 20-2 also gives the cost: a TILELOADDT1 every 33 cycles at best, against one TILELOADD every 8, with latencies of 48 and 45 cycles.

In our builds

The intrinsic is _tile_stream_loadd(tile, base, stride). With -mamx-tile, GCC 14 and Clang 23 at -O2 compile it to tileloaddt1 tmm1, [rdi+rax] with the stride, even a constant 64, moved into a register first, as for TILELOADD. Clang 23’s __tile1024i type has __tile_stream_loadd; in a loop that loads A with it, B with __tile_loadd and multiplies with TDPBUUD, Clang wrote one TILELOADDT1 and one TILELOADD before each TDPBUUD. Zen 5 has no AMX, and this site’s recorded cases include none of TILELOADDT1.

In the optimization guide

What the optimization guide says about TILELOADDT1, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Golden Cove and Raptor Cove

Vectors, AVX-512 and AMX: On Sapphire and Emerald Rapids, a tile multiplication (tdp*) can start every 16 cycles and takes 52; a tile load every 8, taking 45; and loading the tile configuration takes about 204 cycles, worth doing once rather than in every call.
Vectors, AVX-512 and AMX: A tile load cannot take its data from stores still in the store buffer: it waits until they reach the cache.

Forms

Every encoding of TILELOADDT1 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`TILELOADDT1 tmm, sibmem` 64-bit mode only TILELOADDT1_TMMu32_MEMu32	`VEX.LZ.66.0F38.W0 4B /r`	AMX_TILE
`TILELOADDT1 tmm, sibmem` TILELOADDT1_TMMu32_MEMu32_APX	`EVEX.LLZ.66.0F38.W0 4B /r`	APX_F + AMX_TILE

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`tmm, sibmem`
Sapphire Rapids	100 / 0.25p0156

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

on = xcr0 if cr4 >> 18 & 1 else 0    # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 3 != 3:                # TILECFG and TILEDATA
    fault(UD)
if palette != 1:                     # 0: no tiles configured; ACE's
    fault(UD)                        # palette 2 has no loads
if not tmm1.rows or tmm1.colsb % 4:  # left out, or not whole dwords
    fault(UD)
if start_row >= tmm1.rows:
    fault(UD)
if xfd >> 18 & 1:                    # the OS keeps the tiles from
    fault(NM)                        # this thread
a = mem.address                      # row 0: base + displacement
s = mem.stride                       # index * scale, 0 without one
n = tmm1.colsb
for r in range(start_row, tmm1.rows):
    tmm1.row[r] = load(a + r * s, 8 * n)
start_row = 0
# a fault in row r leaves the rows before it loaded and start_row
# = r, where the instruction goes on when it runs again
# a hint: the data is used again, but need not stay in the
# caches nearest the processor
# tmm1 is zeroed past its rows, and the rows loaded past colsb

Not run on a processor: none of these processors has AMX.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`TILELOADDT1 tmm, sibmem` 64-bit mode only
`tmm`	explicit	write
`sibmem`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms: AMX-E3
EVEX forms: AMX-E3-EVEX

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to TILELOADDT1, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_tile_stream_loadd` `void _tile_stream_loadd(const int dst, const void *base, __SIZE_TYPE__ stride)`	`TILELOADDT1 tmm, sibmem` VEX.LZ -mamx-tile

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AMX_TILE` AMX-TILE	AMX_TILE `CPUID.(EAX=07H,ECX=0):EDX[24]` AMX_TILE	Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`APX_F_AMX` APX	APX_F + AMX_TILE `CPUID.(EAX=07H,ECX=1):EDX[21]` APX_F `CPUID.(EAX=07H,ECX=0):EDX[24]` AMX_TILE	Diamond Rapids

More AMX-TILE instructions

More APX instructions

All 88 APX instructions

Keeping the other matrix in L1#

In our builds#