TILEMOVCOL

TILEMOVCOL writes a ZMM register into one column of an ACE tile: tilemovcol tmm1, zmm2, ecx, or with an immediate in place of ECX. Dword r of the register goes to row r, so the 16 dwords of the vector run down the tile, one in each row, in the column that bits 3:0 of ECX or of the immediate name; the other 15 columns keep their values. It is TILEMOVROW’s write form turned on its side, and it goes only one way: no instruction reads a column back out.

Columns of dwords#

Under ACE’s palette 2 a tile has 16 rows of 64 bytes, and the outer products read it as 16 × 16 elements of 32 bits. A column is one dword wide whatever the data; revision 1.16 of the specification corrected its text to that width. All 16 column numbers are valid, and a larger index does not fault: the bits above 3:0 are reserved, to be zero, but nothing checks them. A vector that goes in as a column comes back out as a row, so 16 TILEMOVCOL writes followed by 16 TILEMOVROW reads transpose a 16 × 16 block of dwords without going through memory.

Encoding and checks#

The register form is EVEX opcode 4Bh in map 0F38 with the 66 prefix and W1, the index register in EVEX.vvvv; the immediate form is opcode 2Fh in map 0F3A, again 66 and W1, with vvvv unused and required to be 1111b. TILEMOVROW’s write forms use 4Ah and 07h with the same prefix and W1. The register form has exception class ACE-E6 and the immediate form ACE-E1: 64-bit mode, the tile, scale and AVX-512 state in XCR0 and a loaded tile configuration, or #UD; CR0.TS or bit 18 of IA32_XFD raises #NM. Inside a TSX transaction it aborts the transaction.

In our builds#

GNU as 2.44 and Clang 23.1.2 reject the mnemonic, and neither GCC 14.2.0 nor Clang 23.1.2 has the specification’s _tile_setcol intrinsic, whose index argument the specification names row. By the specification’s encoding, tilemovcol tmm1, zmm2, ecx is 62 F2 F5 48 4B CA, which objdump 2.44 decodes as (bad). No processor at hand has ACE, so this site’s recorded cases include none of TILEMOVCOL.

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

on = xcr0 if cr4 >> 18 & 1 else 0    # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 0xB != 0xB:            # TILECFG, TILEDATA, SCALEDATA
    fault(UD)
if on & 0xE6 != 0xE6:                # AVX-512's state, AVX's and
    fault(UD)                        # SSE's
if palette != 2:                     # ACE's palette alone
    fault(UD)
if cr0 >> 3 & 1 or xfd >> 18 & 1:    # CR0.TS, or the OS keeps the
    fault(NM)                        # tiles from this thread
c = src3 & 15                        # bits 3:0 of imm8 or r32
for r in range(16):                  # dword c of every row
    tmm1.row[r].d[c] = zmm2.d[r]

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

TILEMOVCOL tmm, zmm, imm8 64-bit mode only

ACE-E1

TILEMOVCOL tmm, zmm, r32 64-bit mode only

ACE-E6

Attributes

What else XED records about the forms. How to read.

All forms

may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More ACE instructions

• BSRINIT
• BSRMOVF
• BSRMOVH
• BSRMOVL
• LDTILECFG
• STTILECFG
• TCVTROWD2PS
• TCVTROWPS2BF16H
• TCVTROWPS2BF16L
• TCVTROWPS2PHH
• TCVTROWPS2PHL
• TILEMOVROW
• TILERELEASE
• TILEZERO
• TOP2BF16PS
• TOP4BSSD
• TOP4BSUD
• TOP4BUSD
• TOP4BUUD
• TOP4MXBF8PS
• TOP4MXBHF8PS
• TOP4MXBSSPS
• TOP4MXHBF8PS
• TOP4MXHF8PS