TILEMOVROW

TILEMOVROW copies one row of a tile into a ZMM register,: tilemovrow zmm1, tmm2, ecx or with an immediate row. Bits 3:0 of ECX or of the immediate name the row, and the other bits are ignored. It is the plain member of AMX-AVX512; TCVTROWD2PS and the other TCVTROW instructions convert the row on the way.

No fault for a row that is not there#

A row number at or past the tile’s configured rows is no error: the ZMM register becomes all zeros. So does the part of a row past the configured bytes per row, and the instruction always writes the whole 64 bytes. A short tile thus reads as if padded with zeros. Bytes are copied whole, but the tile’s row width must still be in whole dwords.

The checks combine both register files: 64-bit mode, the tile and AVX-512 state in XCR0, a loaded configuration and a tile that it gives rows. Any of them missing raises #UD; CR0.TS or bit 18 of IA32_XFD raises #NM. The ISE’s TILEMOVROW page gives AMX-E7-EVEX to the register form and AMX-E8-EVEX to the immediate; its TCVTROW pages and XED have them the other way round, and only an immediate form can leave vvvv unused as AMX-E7-EVEX asks. Inside a TSX transaction it aborts the transaction.

ACE’s direction back#

Under the ACE specification, TILEMOVROW also runs the other way, tilemovrow tmm1, zmm2, ecx or with an immediate, with W1 in place of W0, and this write form works only under ACE’s palette 2 with SCALEDATA enabled in XCR0. There every tile has all 16 rows of 64 bytes, so the zeros above never arise, and ACE calls the upper bits of the row number reserved, to be zero. It is how results leave a tile after outer products such as TOP4BSSD, and how data enters one, since palette 2 has no tile loads or stores; TILEMOVCOL writes a column.

In our builds#

GCC 14 has no -mamx-avx512 option. With it, Clang 23 at -O2 compiles _tile_movrow(2, r) to tilemovrow zmm0, tmm2, edi; tilemovrow zmm1, tmm2, ecx is 62 F2 75 48 4A CA. _tile_movrow(2, 5) still goes through a register, mov eax, 5; the immediate form takes _tile_movrowi(2, 5). Neither Clang 23 nor GNU as 2.44 accepted the write form. Zen 5 has no AMX, and this site’s recorded cases include none of TILEMOVROW.

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

on = xcr0 if cr4 >> 18 & 1 else 0    # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 3 != 3:                # TILECFG and TILEDATA
    fault(UD)
if on & 0xE6 != 0xE6:                # AVX-512's state, AVX's and
    fault(UD)                        # SSE's
if palette == 0 or not tmm2.rows:    # no configuration, or a tile it
    fault(UD)                        # leaves out
if tmm2.colsb % 4:                   # whole dwords
    fault(UD)
if cr0 >> 3 & 1 or xfd >> 18 & 1:    # CR0.TS, or the OS keeps the
    fault(NM)                        # tiles from this thread
# ACE's exception class for these forms asks for XCR0 bit 20
# (SCALEDATA) too
r = src3 & 15                        # bits 3:0 of imm8 or r32
v = 0                                # a row past the tile's: zeros
if r < tmm2.rows:                    # bytes past colsb: zeros
    v = low(tmm2.row[r], 8 * tmm2.colsb)
zmm1.write(v)
start_row = 0

on = xcr0 if cr4 >> 18 & 1 else 0    # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 0xB != 0xB:            # TILECFG, TILEDATA, SCALEDATA
    fault(UD)
if on & 0xE6 != 0xE6:                # AVX-512's state, AVX's and
    fault(UD)                        # SSE's
if palette != 2:                     # ACE's palette alone
    fault(UD)
if cr0 >> 3 & 1 or xfd >> 18 & 1:    # CR0.TS, or the OS keeps the
    fault(NM)                        # tiles from this thread
r = src3 & 15                        # bits 3:0 of imm8 or r32
tmm1.row[r] = zmm2                   # under palette 2, all 64 bytes

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

TILEMOVROW zmm, tmm, imm8 64-bit mode only

AMX-E7-EVEX

TILEMOVROW zmm, tmm, r32 64-bit mode only

AMX-E8-EVEX

TILEMOVROW tmm, zmm, imm8 64-bit mode only

ACE-E1

TILEMOVROW tmm, zmm, r32 64-bit mode only

ACE-E6

Attributes

What else XED records about the forms. How to read.

All forms

may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to TILEMOVROW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AMX-AVX512 instructions

• TCVTROWD2PS
• TCVTROWPS2BF16H
• TCVTROWPS2BF16L
• TCVTROWPS2PHH
• TCVTROWPS2PHL

More ACE instructions

• BSRINIT
• BSRMOVF
• BSRMOVH
• BSRMOVL
• LDTILECFG
• STTILECFG
• TCVTROWD2PS
• TCVTROWPS2BF16H
• TCVTROWPS2BF16L
• TCVTROWPS2PHH
• TCVTROWPS2PHL
• TILEMOVCOL
• TILERELEASE
• TILEZERO
• TOP2BF16PS
• TOP4BSSD
• TOP4BSUD
• TOP4BUSD
• TOP4BUUD
• TOP4MXBF8PS
• TOP4MXBHF8PS
• TOP4MXBSSPS
• TOP4MXHBF8PS
• TOP4MXHF8PS