x86-64.net

Instruction

TILERELEASE

Returns the AMX tile configuration and all tile data to their initial state: unconfigured and zero.

Extensions
Forms
1 (1 VEX)
Data
Intel XED v2026.08.23

TILERELEASE puts the AMX tile state back in its initial state: it clears all tile data and the configuration, so palette 0 is selected and no tile is configured, the state that LDTILECFG with palette 0 also leaves. Under ACE it also resets the block-scale register to 7FH in every byte, a scale of 1.0, rather than zero. It takes no operand and changes no flag. A program runs it when it has finished with the tiles: with the state back in its initial configuration, XSAVEC, XSAVEOPT and XSAVES skip the 8 KBytes of tile data instead of writing them out on every save.

Checks

TILERELEASE has the fewest checks of the tile instructions: tile state enabled in XCR0 (bits 18:17) with CR4.OSXSAVE set, 64-bit mode, and VEX.vvvv all ones, or #UD. It needs no loaded configuration, and unlike the instructions that touch tile data it raises no #NM when IA32_XFD bit 18 disables the tiles, so it is safe to run whatever the state. Inside a TSX transaction it aborts the transaction.

In Linux

Linux 7.3 runs TILERELEASE in the kernel before deep idle. Its arch/x86/kernel/fpu/core.c releases the tiles when the processor has AMX and XGETBV with ECX = 1 reports the tile state in use, and drivers/idle/intel_idle.c calls it before entering C6 on Sapphire Rapids and Granite Rapids, where tile state left in use would stand in the way of that idle state. arch/x86/include/asm/special_insns.h writes the instruction as bytes for assemblers older than binutils 2.36.

Not run here

Zen 5 has no AMX, so the probe left TILERELEASE unrun. GCC 14 and Clang 23 compile _tile_release() with -mamx-tile to a single TILERELEASE, VEX.128.NP.0F38.W0 49 C0.

Forms

Every encoding of TILERELEASE that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
TILERELEASE 64-bit mode only TILERELEASEVEX.128.NP.0F38.W0 49 C0ACE v1 or AMX_TILE

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
ModelTILERELEASE
Sapphire Rapids100 / 0.25p0156

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

on = xcr0 if cr4 >> 18 & 1 else 0    # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 3 != 3:                # TILECFG and TILEDATA
    fault(UD)
for t in range(8):                   # TILEDATA's initial state
    tmm[t].write(0)
if palettes >> 2 & 1:                # with ACE, every scale 2^0
    for i in range(128):
        bsr0.b[i] = 0x7F
tilecfg = 0                          # palette 0: no configuration
# IA32_XFD does not stop it (no #NM)

Not run on a processor: none of these processors has AMX.

Operands

None: XED lists no operands for this form.

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AMX-E6

Attributes

What else XED records about the forms. How to read.

All forms
may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to TILERELEASE, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_tile_release void _tile_release(void)

TILERELEASE VEX.128 -mamx-tile

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AMX_TILE_BASE

ACE v1
CPUID.(EAX=07H,ECX=1):ECX[11] ACE
CPUID.(EAX=1DH,ECX=2):EAX[7:0] ≥ 1 ACE version

or

AMX_TILE
CPUID.(EAX=07H,ECX=0):EDX[24] AMX_TILE

Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AMX-TILE instructions

More ACE instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-726 (TILERELEASE)
  5. x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Linux 7.3: arch/x86/include/asm/special_insns.h, drivers/dma/idxd/submit.c and cdev.c, arch/x86/kernel/fpu/core.c and drivers/idle/intel_idle.c (ENQCMDS for Intel's accelerators, TILERELEASE before idle)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.