TILESTORED instruction (AMX-TILE, APX)

TILESTORED writes a tile to memory row by row, the store that matches TILELOADD, and addresses memory the same way: the operand must use a SIB byte, the base plus displacement is where row 0 goes, and the index register, shifted by the scale, is the distance between rows. Each row writes exactly the tile’s configured bytes per row, so with a stride wider than the tile the bytes between rows are left alone: a 16 × 64-byte tile can be stored straight into its place in a larger matrix, such as a block of C in a matrix multiplication.

The stride is a register

The stride cannot be an immediate. In our builds with -mamx-tile, GCC 14 and Clang 23 at -O2 compiled _tile_stored(0, c, 64) to mov eax, 64 and tilestored [rdx+rax], tmm0; with a stride already in a register, they used it directly. The tile number is a constant, as in all of GCC’s and Clang’s _tile_* intrinsics.

Faults and restarts

The tile must be one the configuration gives rows, in whole dwords per row, and like every AMX instruction TILESTORED raises #UD without a tile configuration, outside 64-bit mode, or before the operating system has enabled the tile state in XCR0. A page fault can stop it in the middle: the rows already written stay written, and start_row in the tile configuration records where to go on, so that the instruction continues from that row when it runs again; it raises #UD if start_row is not below the tile’s rows. AMX instructions never raise #AC, whatever the alignment. Under ACE’s palette 2 there is no tile store at all: ACE moves results out of tiles through vector registers, with TILEMOVROW.

Reading the rows back

Intel’s optimization manual says that a tile store can forward its data to a later load other than a tile load only when both are full 64-byte lines, and advises against relying on it: the load should come some tens of cycles later. A tile load cannot take data from stores still in the store buffer at all (Section 20.15).

Forms

Every encoding of TILESTORED that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`TILESTORED sibmem, tmm` 64-bit mode only TILESTORED_MEMu32_TMMu32	`VEX.LZ.F3.0F38.W0 4B /r`	AMX_TILE
`TILESTORED sibmem, tmm` TILESTORED_MEMu32_TMMu32_APX	`EVEX.LLZ.F3.0F38.W0 4B /r`	APX_F + AMX_TILE

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`sibmem, tmm`
Sapphire Rapids	100 / 0.25p0156

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

on = xcr0 if cr4 >> 18 & 1 else 0    # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 3 != 3:                # TILECFG and TILEDATA
    fault(UD)
if palette != 1:                     # 0: no tiles configured; ACE's
    fault(UD)                        # palette 2 has no stores
if not tmm2.rows or tmm2.colsb % 4:  # left out, or not whole dwords
    fault(UD)
if start_row >= tmm2.rows:
    fault(UD)
if xfd >> 18 & 1:                    # the OS keeps the tiles from
    fault(NM)                        # this thread
a = mem.address                      # row 0: base + displacement
s = mem.stride                       # index * scale, 0 without one
n = tmm2.colsb
for r in range(start_row, tmm2.rows):
    store(a + r * s, 8 * n, tmm2.row[r])
start_row = 0
# a fault in row r leaves the rows before it stored and start_row
# = r, where the instruction goes on when it runs again

Not run on a processor: none of these processors has AMX.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`TILESTORED sibmem, tmm` 64-bit mode only
`sibmem`	explicit	write
`tmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms: AMX-E3
EVEX forms: AMX-E3-EVEX

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to TILESTORED, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_tile_stored` `void _tile_stored(const int dst, void *base, __SIZE_TYPE__ stride)`	`TILESTORED sibmem, tmm` VEX.LZ -mamx-tile

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AMX_TILE` AMX-TILE	AMX_TILE `CPUID.(EAX=07H,ECX=0):EDX[24]` AMX_TILE	Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`APX_F_AMX` APX	APX_F + AMX_TILE `CPUID.(EAX=07H,ECX=1):EDX[21]` APX_F `CPUID.(EAX=07H,ECX=0):EDX[24]` AMX_TILE	Diamond Rapids

More AMX-TILE instructions

More APX instructions

All 88 APX instructions

The stride is a register#

Faults and restarts#

Reading the rows back#