TILEZERO

TILEZERO clears one tile register, the usual first step for an accumulator: before the dot products of a new block of C, such as TDPBSSD or TDPBF16PS, add into it. Intel’s manual has it clear the whole register, all 16 rows of 64 bytes, whatever shape the configuration gives the tile; since the bytes outside a tile’s shape are zero anyway, the effect is the same.

Its checks are the fewest of the tile instructions: tile state enabled in XCR0, 64-bit mode, a loaded configuration, and a tile that the configuration gives rows; bit 18 of IA32_XFD set raises #NM. Unlike the loads, stores and multiplications, it does not care how wide the tile’s rows are, and it is one of the few AMX instructions that also work under the ACE palette 2, where tiles hold the results of outer products such as TOP4BSSD.

When it is not needed#

LDTILECFG zeroes all tile data as it loads a configuration, and TILERELEASE returns the tiles to their initial state, so code that configures the tiles and then fills each accumulator once needs no TILEZERO for that first block. An accumulator may also start from data: loading the old C with TILELOADD instead adds the product to it.

In compiled code#

With -mamx-tile, GCC 14 and Clang 23 at -O2 compile _tile_zero(0) to tilezero tmm0. Clang 23’s tile type __tile1024i has __tile_zero(&c), which compiled to a TILEZERO of the register Clang chose for c.

A use beside AVX-512#

Intel’s optimization manual counts TILEZERO as an AMX compute instruction for the processor’s port management: while AMX compute instructions run, the processor closes one of its two AVX-512 FMA ports, and reopening it costs a few cycles each time. Between AMX blocks separated by about 100 to 300 AVX-512 instructions, the manual suggests one or two TILEZEROs in the middle of the AVX-512 code, about 100 instructions apart, to keep the port closed (Section 20.11.3).

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

on = xcr0 if cr4 >> 18 & 1 else 0    # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 3 != 3:                # TILECFG and TILEDATA
    fault(UD)
if palette == 0 or not tmm1.rows:    # no configuration, or a tile it
    fault(UD)                        # leaves out
if xfd >> 18 & 1:                    # the OS keeps the tiles from
    fault(NM)                        # this thread
tmm1.write(0)                        # all 16 rows of 64 bytes
start_row = 0

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AMX-E5

Attributes

What else XED records about the forms. How to read.

All forms

may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to TILEZERO, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AMX-TILE instructions

• LDTILECFG
• STTILECFG
• TILELOADD
• TILELOADDT1
• TILERELEASE
• TILESTORED

More ACE instructions

• BSRINIT
• BSRMOVF
• BSRMOVH
• BSRMOVL
• LDTILECFG
• STTILECFG
• TCVTROWD2PS
• TCVTROWPS2BF16H
• TCVTROWPS2BF16L
• TCVTROWPS2PHH
• TCVTROWPS2PHL
• TILEMOVCOL
• TILEMOVROW
• TILERELEASE
• TOP2BF16PS
• TOP4BSSD
• TOP4BSUD
• TOP4BUSD
• TOP4BUUD
• TOP4MXBF8PS
• TOP4MXBHF8PS
• TOP4MXBSSPS
• TOP4MXHBF8PS
• TOP4MXHF8PS