Instruction
TILEZERO
Sets every byte of a tile register to zero.
Forms
| Instruction | Encoding | Requires |
|---|---|---|
TILEZERO tmm 64-bit mode only
TILEZERO_TMMu32 | VEX.LZ.F2.0F38.W0 49 /r | ACE v1 or AMX_TILE |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to TILEZERO, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_tile_zero
void _tile_zero(const int tile) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AMX_TILE_BASE | ACE v1 or AMX_TILE | Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
More AMX-TILE instructions
More ACE instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
- x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.