TLBSYNC instruction (INVLPGB)

Forms

Every encoding of TLBSYNC that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`TLBSYNC` TLBSYNC	`NP 0F 01 FF`	INVLPGB

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if CPL > 0:
    fault(GP, 0)
pass                             # waits until every processor has
                                 # done the INVLPGBs of this one, and
                                 # the stores through the dropped
                                 # translations are out

Not run on a processor: XED gives TLBSYNC no CPUID bit by which the probe could skip it where the processor lacks INVLPGB (CPUID Fn8000_0008_EBX[3]).

Operands

None: XED lists no operands for this form.

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms: privileged: CPL 0 only

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AMD_INVLPGB` INVLPGB	INVLPGB `CPUID.80000008H:EBX[3]` INVLPGB	Zen 3, Zen 4, Zen 5, Zen 6 Note: Only the EPYC server processors have INVLPGB and TLBSYNC: AMD's references for the Ryzen processors of Zen 3, Zen 4 and Zen 5 leave CPUID_Fn80000008_EBX[INVLPGB] (bit 3) clear. Zen 6 is listed because Zen 5 has them, until AMD publishes a Processor Programming Reference for Zen 6.

More INVLPGB instructions

INVLPGB