x86-64.net

Instruction

TOP2BF16PS

ACE rank-2 outer product: adds the dot product of each bfloat16 pair of one ZMM source with each pair of the other to a single-precision tile.

Extensions
Forms
1 (1 EVEX)
Data
Intel XED v2026.08.23

TOP2BF16PS is the bfloat16 outer product of ACE: top2bf16ps tmm1, zmm2, zmm3 adds to the single at row i and column j of the tile the two products of the bfloat16 pair in dword i of zmm2 with the pair in dword j of zmm3, low half with low half and high half with high half. That is a rank-2 step, 512 products from two registers, where the byte outer products such as TOP4BSSD are rank 4. A matrix product of depth K takes K/2 of them: each register of A holds one pair of each of 16 rows, A transposed in dwords, and each register of B one pair of each of 16 columns, two of its rows interleaved.

Two roundings for each pair

The two products are added exactly and their sum is rounded once to a single; that single is then added to the old element with a second rounding, both to nearest even. The accumulator thus takes one rounding per pair, where VDPBF16PS adds its two products one at a time. That page’s Zen 5 case of 1.0 + 2^-24 + 2^-24, which VDPBF16PS left at 1.0, comes out of TOP2BF16PS as 1 + 2^-23 (3F800001H), since the products sum to 2^-23 before they meet the accumulator. AMX’s TDPBF16PS keeps separate sums of the low and of the high products over a whole row, a third order.

Fixed arithmetic

MXCSR is neither read nor written, and nothing is flagged. Bfloat16 inputs that are denormal count as zeros, so does a denormal single in the tile, and a sum too small for a normal single becomes zero: two products of 2^-140 leave a non-zero element as it was. A NaN among the inputs, or infinity times zero, gives the QNaN indefinite FFC00000H. There is no block scaling and no immediate.

In our builds

GNU as 2.44 and Clang 23.1.2 reject the mnemonic, and neither GCC 14.2.0 nor Clang 23.1.2 has ACE’s _tile_top2bf16ps intrinsic. The encoding is EVEX opcode 5Ch in map 0F38 with the F3 prefix and W0: the tile in ModRM.reg, zmm2 in ModRM.rm and zmm3 in EVEX.vvvv, under exception class ACE-E4. No processor at hand has ACE, so this site’s recorded cases include none of TOP2BF16PS.

Forms

Every encoding of TOP2BF16PS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
TOP2BF16PS tmm, zmm, zmm 64-bit mode only TOP2BF16PS_TMMf32_ZMMbf16_ZMMbf16EVEX.512.F3.0F38.W0 5C /rACE v1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

on = xcr0 if cr4 >> 18 & 1 else 0    # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 0xB != 0xB:            # TILECFG, TILEDATA, SCALEDATA
    fault(UD)
if on & 0xE6 != 0xE6:                # AVX-512's state, AVX's and
    fault(UD)                        # SSE's
if palette != 2:                     # ACE's palette alone
    fault(UD)
if cr0 >> 3 & 1 or xfd >> 18 & 1:    # CR0.TS, or the OS keeps the
    fault(NM)                        # tiles from this thread
for i in range(16):                  # row i: pair i of zmm2
    for j in range(16):              # column j: pair j of zmm3
        a = zmm2.bf16[2 * i]
        b = zmm3.bf16[2 * j]
        p = mul_exact(a, b)          # the low halves
        a = zmm2.bf16[2 * i + 1]
        b = zmm3.bf16[2 * j + 1]
        q = mul_exact(a, b)          # the high halves
        r = round_ftz(add_exact(p, q), 0)
        c = tmm1.row[i].f32[j]
        t = add_exact(c, r)
        tmm1.row[i].f32[j] = round_ftz(t, 0)

Not run on a processor: none of these processors has ACE.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
TOP2BF16PS tmm, zmm, zmm 64-bit mode only
tmmexplicitread, write
zmmexplicitread
zmmexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
ACE-E4

Attributes

What else XED records about the forms. How to read.

All forms
may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
ACE_1

ACE v1
CPUID.(EAX=07H,ECX=1):ECX[11] ACE
CPUID.(EAX=1DH,ECX=2):EAX[7:0] ≥ 1 ACE version

None in XED’s chip model, which lists these instructions only under its placeholder for future processors.

More ACE instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.