TOP4BSSD instruction (ACE)

TOP4BSSD is the basic ACE outer product. Both sources are ZMM registers of 16 dwords, each dword holding four signed bytes. For every row i and column j of the destination tile, it adds the dot product of dword i of the first source and dword j of the second (four byte products) to the 32-bit integer at (i, j): a 16 × 16 update of the whole tile, 1024 multiplications.

A matrix multiplication loop therefore loads a vector holding a 16 × 4 slice of A and one holding a 4 × 16 slice of B for each step of four along the shared dimension, and after the last step moves the finished 16 × 16 block out with TILEMOVROW. The signed and unsigned variants are TOP4BSUD, TOP4BUSD and TOP4BUUD; the first letter after TOP4B gives the type of the first source.

Forms

Every encoding of TOP4BSSD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`TOP4BSSD tmm, zmm, zmm` 64-bit mode only TOP4BSSD_TMMu32_ZMMi8_ZMMi8	`EVEX.512.F2.0F38.W0 5E /r`	ACE v1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

on = xcr0 if cr4 >> 18 & 1 else 0    # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 0xB != 0xB:            # TILECFG, TILEDATA, SCALEDATA
    fault(UD)
if on & 0xE6 != 0xE6:                # AVX-512's state, AVX's and
    fault(UD)                        # SSE's
if palette != 2:                     # ACE's palette alone
    fault(UD)
if cr0 >> 3 & 1 or xfd >> 18 & 1:    # CR0.TS, or the OS keeps the
    fault(NM)                        # tiles from this thread
for i in range(16):                  # row i: dword i of zmm2
    for j in range(16):              # column j: dword j of zmm3
        s = tmm1.row[i].d[j]
        for k in range(4):
            a = zmm2.sb[4 * i + k]
            s += a * zmm3.sb[4 * j + k]
        tmm1.row[i].d[j] = s         # modulo 2^32

Not run on a processor: none of these processors has ACE.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`TOP4BSSD tmm, zmm, zmm` 64-bit mode only
`tmm`	explicit	read, write
`zmm`	explicit	read
`zmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: ACE-E4

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`ACE_1` ACE	ACE v1 `CPUID.(EAX=07H,ECX=1):ECX[11]` ACE `CPUID.(EAX=1DH,ECX=2):EAX[7:0] ≥ 1` ACE version	None in XED’s chip model, which lists these instructions only under its placeholder for future processors.

TOP4BSSD