x86-64.net

Instruction

TOP4BSUD

ACE outer product of a ZMM register of signed bytes with one of unsigned bytes, four per dword, accumulated into a tile of 32-bit integers.

Extensions
Forms
1 (1 EVEX)
Data
Intel XED v2026.08.23

TOP4BSUD is TOP4BSSD with unsigned bytes in its second source: for every row i and column j of the tile it adds the four products of the signed bytes of dword i of zmm2 with the unsigned bytes of dword j of zmm3 to the 32-bit integer at (i, j). TOP4BSSD’s page covers the outer product and how a matrix product is built from it; this page covers what the signedness changes. The order is that of AMX’s TDPBSUD and of VPDPBSUD in AVX-VNNI-INT8: signed first, unsigned second.

How far the sums reach

Each product lies between -32,640 (-128 times 255) and 32,385 (127 times 255), so one instruction moves an element by at most 130,560, twice as far as TOP4BSSD, whose four products stay between -65,024 and 65,536. The tile adds modulo 2^32, with no saturation. An accumulator that starts at zero therefore stays inside the signed 32-bit range for 16,448 instructions, a depth of 65,792 bytes along K, against 32,767 instructions for TOP4BSSD; a longer sum has to be split into blocks that are added in a wider type.

Encoding

EVEX opcode 5Eh in map 0F38 with W0 and the F3 prefix; F2, 66 and no prefix give TOP4BSSD, TOP4BUSD and TOP4BUUD, the same prefixes that tell TDPBSSD and its siblings apart in VEX. The tile is in ModRM.reg, zmm2 in ModRM.rm and zmm3 in EVEX.vvvv, so by the specification’s encoding top4bsud tmm0, zmm1, zmm2 is 62 F2 6E 48 5E C1. The exception class is ACE-E4, as for every outer product.

In our builds

GNU as 2.44 and Clang 23.1.2 reject the mnemonic, neither GCC 14.2.0 nor Clang 23.1.2 has ACE’s _tile_top4bsud intrinsic, and objdump 2.44 decodes those bytes as (bad). No processor at hand has ACE, so this site’s recorded cases include none of TOP4BSUD.

Forms

Every encoding of TOP4BSUD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
TOP4BSUD tmm, zmm, zmm 64-bit mode only TOP4BSUD_TMMu32_ZMMi8_ZMMu8EVEX.512.F3.0F38.W0 5E /rACE v1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

on = xcr0 if cr4 >> 18 & 1 else 0    # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 0xB != 0xB:            # TILECFG, TILEDATA, SCALEDATA
    fault(UD)
if on & 0xE6 != 0xE6:                # AVX-512's state, AVX's and
    fault(UD)                        # SSE's
if palette != 2:                     # ACE's palette alone
    fault(UD)
if cr0 >> 3 & 1 or xfd >> 18 & 1:    # CR0.TS, or the OS keeps the
    fault(NM)                        # tiles from this thread
for i in range(16):                  # row i: dword i of zmm2
    for j in range(16):              # column j: dword j of zmm3
        s = tmm1.row[i].d[j]
        for k in range(4):
            a = zmm2.sb[4 * i + k]
            s += a * zmm3.b[4 * j + k]
        tmm1.row[i].d[j] = s         # modulo 2^32

Not run on a processor: none of these processors has ACE.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
TOP4BSUD tmm, zmm, zmm 64-bit mode only
tmmexplicitread, write
zmmexplicitread
zmmexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
ACE-E4

Attributes

What else XED records about the forms. How to read.

All forms
may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
ACE_1

ACE v1
CPUID.(EAX=07H,ECX=1):ECX[11] ACE
CPUID.(EAX=1DH,ECX=2):EAX[7:0] ≥ 1 ACE version

None in XED’s chip model, which lists these instructions only under its placeholder for future processors.

More ACE instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.