x86-64.net

Instruction

TOP4MXBF8PS

ACE outer product of E5M2 FP8 vectors (OCP microscaling), scaled by the block scale register and added to a single-precision tile.

Extensions
Forms
1 (1 EVEX)
Data
Intel XED v2026.08.23

TOP4MXBF8PS is TOP4MXHF8PS with E5M2 values, which the mnemonic calls BF8, in both sources: element (i, j) of the tile gains the sum of the four products of dword i of zmm2 with dword j of zmm3, multiplied by the row’s and the column’s scales from the block scale register that the immediate selects. That page covers the scales, the single rounding of the scaled sum and the second rounding into the tile. AMX-FP8’s TDPBF8PS multiplies the same format tile by tile, without scales.

Range and infinities

E5M2 runs from 2^-16, its smallest denormal, to 57,344. Its products thus range from 2^-32 to over 3.2 × 10^9, and the specification sums the four in a 128-bit integer with 2^-32 as its unit, so nothing is lost before the one rounding. A sum of four products stays under 2^34, but large scales can carry it past the largest single.

E5M2 also has infinities, 7CH and FCH, which E4M3 lacks. The format table of ACE 1.16.2 lists none for E5M2, but its NaNs leave those two encodings out, and the outer product’s rules handle infinite inputs: infinity times a non-zero number is an infinity, while infinity times zero and the sum of infinities of both signs give the QNaN indefinite FFC00000H, as do NaNs (7DH to 7FH and FDH to FFH) and scales of FFH. With +infinity (7CH) in A’s dword, 1.0 (3CH) at the same place in B’s and the other bytes zero, a finite element becomes +infinity; with 00H, a zero, in place of the 1.0 it becomes FFC00000H.

In our builds

GNU as 2.44 and Clang 23.1.2 reject the mnemonic, and neither GCC 14.2.0 nor Clang 23.1.2 has ACE’s _tile_top4mxbf8ps intrinsic. The encoding is EVEX opcode 8Dh in map 0F3A with W0 and no prefix, under exception class ACE-E4. No processor at hand has ACE, so this site’s recorded cases include none of TOP4MXBF8PS.

Forms

Every encoding of TOP4MXBF8PS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
TOP4MXBF8PS tmm, zmm, zmm, imm8 64-bit mode only TOP4MXBF8PS_TMMf32_ZMMbf8_ZMMbf8_IMM8EVEX.512.NP.0F3A.W0 8D /r ibACE v1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

on = xcr0 if cr4 >> 18 & 1 else 0    # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 0xB != 0xB:            # TILECFG, TILEDATA, SCALEDATA
    fault(UD)
if on & 0xE6 != 0xE6:                # AVX-512's state, AVX's and
    fault(UD)                        # SSE's
if palette != 2:                     # ACE's palette alone
    fault(UD)
if cr0 >> 3 & 1 or xfd >> 18 & 1:    # CR0.TS, or the OS keeps the
    fault(NM)                        # tiles from this thread
ga = imm8 & 3                        # the group of A's scales
gb = imm8 >> 3 & 3                   # and of B's
for i in range(16):                  # row i: dword i of zmm2
    sa = bsr0.b[64 + 4 * i + ga]     # 2^(sa - 127)
    for j in range(16):              # column j: dword j of zmm3
        sb = bsr0.b[4 * j + gb]
        s = 0                        # the exact sum
        for k in range(4):
            a = zmm2.bf8[4 * i + k]
            b = zmm3.bf8[4 * j + k]
            p = mul_exact(a, b)
            s = add_exact(s, p)
        c = tmm1.row[i].f32[j]
        r = round_ftz(s, sa + sb - 254)
        t = round_ftz(add_exact(c, r), 0)
        if sa == 0xFF or sb == 0xFF:  # a scale that is a NaN
            t = 0xFFC00000           # the QNaN indefinite
        tmm1.row[i].d[j] = t

Not run on a processor: none of these processors has ACE.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
TOP4MXBF8PS tmm, zmm, zmm, imm8 64-bit mode only
tmmexplicitread, write
zmmexplicitread
zmmexplicitread
imm8explicitread
BSR0implicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
ACE-E4

Attributes

What else XED records about the forms. How to read.

All forms
may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
ACE_1

ACE v1
CPUID.(EAX=07H,ECX=1):ECX[11] ACE
CPUID.(EAX=1DH,ECX=2):EAX[7:0] ≥ 1 ACE version

None in XED’s chip model, which lists these instructions only under its placeholder for future processors.

More ACE instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.