x86-64.net

Instruction

TOP4MXBHF8PS

ACE outer product of E5M2 by E4M3 FP8 vectors (OCP microscaling), scaled by the block scale register and added to a single-precision tile.

Extensions
Forms
1 (1 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of TOP4MXBHF8PS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
TOP4MXBHF8PS tmm, zmm, zmm, imm8 64-bit mode only TOP4MXBHF8PS_TMMf32_ZMMbf8_ZMMhf8_IMM8EVEX.512.F2.0F3A.W0 8D /r ibACE v1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
ACE_1

ACE v1
CPUID.(EAX=07H,ECX=1):ECX[11] ACE
CPUID.(EAX=1DH,ECX=2):EAX[7:0] ≥ 1 ACE version

None yet: XED lists these instructions only under its placeholder for future processors.

More ACE instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.