x86-64.net

Instruction

TOP4MXBHF8PS

ACE outer product of E5M2 by E4M3 FP8 vectors (OCP microscaling), scaled by the block scale register and added to a single-precision tile.

Extensions
Forms
1 (1 EVEX)
Data
Intel XED v2026.08.23

TOP4MXBHF8PS is the mixed-format FP8 outer product of ACE with E5M2 (BF8) values in its first source and E4M3 (HF8) values in its second: element (i, j) of the tile gains the four products of dword i of zmm2, A’s row i, with dword j of zmm3, B’s column j, summed exactly, multiplied by the two scales the immediate selects, rounded once to a single and added to the old element with a second rounding. TOP4MXHF8PS’s page covers those steps; the letters after MX name A’s format, then B’s. AMX-FP8 has the same pair as TDPBHF8PS, tile by tile and without scales.

Products of two formats

An E5M2 value times an E4M3 value lies between 2^-25, the product of the two smallest denormals, and 57,344 times 448, under 2^25, so a sum of four needs a fixed-point integer of about 52 bits before its one rounding. Only A’s values can be infinite: E4M3 has no infinity, and an infinity in A times a zero in B gives the QNaN indefinite FFC00000H, as do NaNs in either format and a scale of FFH.

The mirror form

Swapping the registers swaps the formats: TOP4MXHBF8PS with zmm3 first and zmm2 second adds to element (j, i) what TOP4MXBHF8PS adds to (i, j), the transposed update. The scales do not follow the registers, though. A’s scales always come from the upper half of the block scale register and B’s from the lower half, so the swap also needs the two halves exchanged, with BSRMOVH and BSRMOVL, and the two fields of the immediate, bits 1:0 and 4:3, exchanged with them.

In our builds

GNU as 2.44 and Clang 23.1.2 reject the mnemonic, and neither GCC 14.2.0 nor Clang 23.1.2 has ACE’s _tile_top4mxbhf8ps intrinsic. The encoding is EVEX opcode 8Dh in map 0F3A with W0 and the F2 prefix, under exception class ACE-E4. No processor at hand has ACE, so this site’s recorded cases include none of TOP4MXBHF8PS.

Forms

Every encoding of TOP4MXBHF8PS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
TOP4MXBHF8PS tmm, zmm, zmm, imm8 64-bit mode only TOP4MXBHF8PS_TMMf32_ZMMbf8_ZMMhf8_IMM8EVEX.512.F2.0F3A.W0 8D /r ibACE v1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

on = xcr0 if cr4 >> 18 & 1 else 0    # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 0xB != 0xB:            # TILECFG, TILEDATA, SCALEDATA
    fault(UD)
if on & 0xE6 != 0xE6:                # AVX-512's state, AVX's and
    fault(UD)                        # SSE's
if palette != 2:                     # ACE's palette alone
    fault(UD)
if cr0 >> 3 & 1 or xfd >> 18 & 1:    # CR0.TS, or the OS keeps the
    fault(NM)                        # tiles from this thread
ga = imm8 & 3                        # the group of A's scales
gb = imm8 >> 3 & 3                   # and of B's
for i in range(16):                  # row i: dword i of zmm2
    sa = bsr0.b[64 + 4 * i + ga]     # 2^(sa - 127)
    for j in range(16):              # column j: dword j of zmm3
        sb = bsr0.b[4 * j + gb]
        s = 0                        # the exact sum
        for k in range(4):
            a = zmm2.bf8[4 * i + k]
            b = zmm3.hf8[4 * j + k]
            p = mul_exact(a, b)
            s = add_exact(s, p)
        c = tmm1.row[i].f32[j]
        r = round_ftz(s, sa + sb - 254)
        t = round_ftz(add_exact(c, r), 0)
        if sa == 0xFF or sb == 0xFF:  # a scale that is a NaN
            t = 0xFFC00000           # the QNaN indefinite
        tmm1.row[i].d[j] = t

Not run on a processor: none of these processors has ACE.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
TOP4MXBHF8PS tmm, zmm, zmm, imm8 64-bit mode only
tmmexplicitread, write
zmmexplicitread
zmmexplicitread
imm8explicitread
BSR0implicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
ACE-E4

Attributes

What else XED records about the forms. How to read.

All forms
may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
ACE_1

ACE v1
CPUID.(EAX=07H,ECX=1):ECX[11] ACE
CPUID.(EAX=1DH,ECX=2):EAX[7:0] ≥ 1 ACE version

None in XED’s chip model, which lists these instructions only under its placeholder for future processors.

More ACE instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.