Instruction
TOP4MXBSSPS
ACE outer product of two ZMM registers of MX INT8 values, scaled by the block scale register and accumulated into a single-precision tile.
- Extensions
- Forms
- 1 (1 EVEX)
- Data
- Intel XED v2026.08.23
TOP4MXBSSPS is the MX INT8 outer product of ACE:
top4mxbssps tmm1, zmm2, zmm3, imm8 multiplies the four signed bytes of
dword i of zmm2 by those of dword j of zmm3, as
TOP4BSSD does, but scales the sum and adds it to a
single at (i, j) of the tile instead of an integer. MXB, microscaling
byte, is the OCP format whose bytes stand for their value times 2^-6, so
40H is 1.0 and the products carry 2^-12. The immediate picks the scales
from the block scale register as for TOP4MXHF8PS:
bits 1:0 the group of A’s, bits 4:3 that of B’s.
An exact sum
The four integer products add up to between -65,024 and 65,536, at most 17 bits and a sign, so the sum times 2^-12 and the two scales, 2^(a + b - 266) in all for scales a and b, fits a single exactly. The first rounding thus changes nothing unless the scales push the value below the normal singles, where it becomes zero, or beyond the largest. Only the addition to the old element rounds, to nearest even, with MXCSR neither read nor written and nothing flagged, and a denormal element counting as zero. The integer form TOP4BSSD gives the same sums exactly in its dwords; this form trades that exactness in the accumulator for the scales and a single’s range.
The bytes have no NaN or infinity. The QNaN indefinite FFC00000H comes only from a scale of FFH or from a NaN already in the tile.
The value of 80H
ACE’s format table gives MX INT8 a range from -1 63/64 (81H) to +1 63/64 (7FH), but the operation sign-extends every byte, so 80H counts as -128, that is -2.0, and the sum can reach 65,536 only through it.
In our builds
GNU as 2.44 and Clang 23.1.2 reject the mnemonic, and neither GCC 14.2.0
nor Clang 23.1.2 has ACE’s _tile_top4mxbssps intrinsic. The encoding
is EVEX opcode 8Fh in map 0F3A with W0 and the F2 prefix, beside the FP8
forms’ 8Dh, under exception class ACE-E4. No
processor at hand has ACE, so this site’s recorded cases include none of
TOP4MXBSSPS.
Forms
| Instruction | Encoding | Requires |
|---|---|---|
TOP4MXBSSPS tmm, zmm, zmm, imm8 64-bit mode only
TOP4MXBSSPS_TMMf32_ZMMi8_ZMMi8_IMM8 | EVEX.512.F2.0F3A.W0 8F /r ib | ACE v1 |
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
on = xcr0 if cr4 >> 18 & 1 else 0 # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 0xB != 0xB: # TILECFG, TILEDATA, SCALEDATA
fault(UD)
if on & 0xE6 != 0xE6: # AVX-512's state, AVX's and
fault(UD) # SSE's
if palette != 2: # ACE's palette alone
fault(UD)
if cr0 >> 3 & 1 or xfd >> 18 & 1: # CR0.TS, or the OS keeps the
fault(NM) # tiles from this thread
ga = imm8 & 3 # the group of A's scales
gb = imm8 >> 3 & 3 # and of B's
for i in range(16): # row i: dword i of zmm2
sa = bsr0.b[64 + 4 * i + ga] # 2^(sa - 127)
for j in range(16): # column j: dword j of zmm3
sb = bsr0.b[4 * j + gb]
s = 0 # the exact sum
for k in range(4):
a = zmm2.sb[4 * i + k]
s += a * zmm3.sb[4 * j + k]
c = tmm1.row[i].f32[j]
r = round_ftz(s, sa + sb - 266) # 2^-12, and the scales
t = round_ftz(add_exact(c, r), 0)
if sa == 0xFF or sb == 0xFF: # a scale that is a NaN
t = 0xFFC00000 # the QNaN indefinite
tmm1.row[i].d[j] = tNot run on a processor: none of these processors has ACE.
Operands
| Operand | Kind | Action |
|---|---|---|
TOP4MXBSSPS tmm, zmm, zmm, imm8 64-bit mode only | ||
tmm | explicit | read, write |
zmm | explicit | read |
zmm | explicit | read |
imm8 | explicit | read |
BSR0 | implicit | read |
Flags
None: XED records no flag that the forms test or change.
Exceptions
The exception class is XED's name for the set of exception conditions that a form follows. How to read.
- All forms
ACE-E4
Attributes
What else XED records about the forms. How to read.
- All forms
- may abort a TSX transaction
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
ACE_1 | ACE v1 | None in XED’s chip model, which lists these instructions only under its placeholder for future processors. |
More ACE instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.