TOP4MXHBF8PS instruction (ACE)

TOP4MXHBF8PS is the mixed-format FP8 outer product of ACE with E4M3 (HF8) values in its first source and E5M2 (BF8) values in its second: element (i, j) of the tile gains the four products of dword i of zmm2 with dword j of zmm3, summed exactly, scaled by the row’s and the column’s scales from the block scale register, rounded once to a single and added to the old element with a second rounding. TOP4MXHF8PS’s page covers those steps, and TOP4MXBHF8PS’s the range of the mixed products and why swapping the two forms also means swapping the scales. AMX-FP8’s counterpart is TDPHBF8PS.

One value, a whole column

Here only B can hold infinities, 7CH and FCH. An outer product uses each dword of a source in 16 elements: dword j of zmm3 meets every row of A in column j of the tile. So one infinite byte in B’s dword j makes the whole column infinite, except in the rows where the matching byte of A is a zero, which give the QNaN indefinite FFC00000H, as infinities of both signs in one sum do. A NaN in A’s dword i spoils row i of the tile in the same way, and a scale of FFH the row or column it belongs to. Each later outer product adds to these elements and leaves them infinite or NaN, so a single bad input value is visible as a full row or column of the result.

In our builds

GNU as 2.44 and Clang 23.1.2 reject the mnemonic, and neither GCC 14.2.0 nor Clang 23.1.2 has ACE’s _tile_top4mxhbf8ps intrinsic. The encoding is EVEX opcode 8Dh in map 0F3A with W0 and the F3 prefix, under exception class ACE-E4. No processor at hand has ACE, so this site’s recorded cases include none of TOP4MXHBF8PS.

Forms

Every encoding of TOP4MXHBF8PS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`TOP4MXHBF8PS tmm, zmm, zmm, imm8` 64-bit mode only TOP4MXHBF8PS_TMMf32_ZMMhf8_ZMMbf8_IMM8	`EVEX.512.F3.0F3A.W0 8D /r ib`	ACE v1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

on = xcr0 if cr4 >> 18 & 1 else 0    # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 0xB != 0xB:            # TILECFG, TILEDATA, SCALEDATA
    fault(UD)
if on & 0xE6 != 0xE6:                # AVX-512's state, AVX's and
    fault(UD)                        # SSE's
if palette != 2:                     # ACE's palette alone
    fault(UD)
if cr0 >> 3 & 1 or xfd >> 18 & 1:    # CR0.TS, or the OS keeps the
    fault(NM)                        # tiles from this thread
ga = imm8 & 3                        # the group of A's scales
gb = imm8 >> 3 & 3                   # and of B's
for i in range(16):                  # row i: dword i of zmm2
    sa = bsr0.b[64 + 4 * i + ga]     # 2^(sa - 127)
    for j in range(16):              # column j: dword j of zmm3
        sb = bsr0.b[4 * j + gb]
        s = 0                        # the exact sum
        for k in range(4):
            a = zmm2.hf8[4 * i + k]
            b = zmm3.bf8[4 * j + k]
            p = mul_exact(a, b)
            s = add_exact(s, p)
        c = tmm1.row[i].f32[j]
        r = round_ftz(s, sa + sb - 254)
        t = round_ftz(add_exact(c, r), 0)
        if sa == 0xFF or sb == 0xFF:  # a scale that is a NaN
            t = 0xFFC00000           # the QNaN indefinite
        tmm1.row[i].d[j] = t

Not run on a processor: none of these processors has ACE.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`TOP4MXHBF8PS tmm, zmm, zmm, imm8` 64-bit mode only
`tmm`	explicit	read, write
`zmm`	explicit	read
`zmm`	explicit	read
`imm8`	explicit	read
`BSR0`	implicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: ACE-E4

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`ACE_1` ACE	ACE v1 `CPUID.(EAX=07H,ECX=1):ECX[11]` ACE `CPUID.(EAX=1DH,ECX=2):EAX[7:0] ≥ 1` ACE version	None in XED’s chip model, which lists these instructions only under its placeholder for future processors.

TOP4MXHBF8PS

One value, a whole column

In our builds

Forms

Operation

Operands

Flags

Exceptions

Attributes

CPUID and processors

More ACE instructions

Sources

One value, a whole column#

In our builds#

Forms

Operation

Operands

Flags

Exceptions

Attributes

CPUID and processors

More ACE instructions

Sources

One value, a whole column

In our builds