x86-64.net

Instruction

TOP4MXHF8PS

ACE outer product of E4M3 FP8 vectors (OCP microscaling), scaled by the block scale register and added to a single-precision tile.

Extensions
Forms
1 (1 EVEX)
Data
Intel XED v2026.08.23

TOP4MXHF8PS is the microscaling FP8 outer product of ACE with E4M3 (HF8) values in both sources: top4mxhf8ps tmm1, zmm2, zmm3, imm8. For row i and column j of the tile it multiplies the four values of dword i of zmm2 by the four of dword j of zmm3, sums the products, multiplies the sum by a scale for row i and one for column j, and adds the result to the single at (i, j), in the shape of TOP4BSSD.

Scales picked by the immediate

The scales come from the 1024-bit block scale register that BSRMOVF loads, each an E8M0 byte standing for 2^(e - 127). Bits 1:0 of the immediate pick one of four groups of A scales, in bytes 64 to 127, and bits 4:3 one of four groups of B scales, in bytes 0 to 63; row i’s scale is byte 4i + group of its half, so the scales line up with the dwords of the data. The other bits are reserved but not checked. With every scale at 7FH, as BSRINIT leaves them, the instruction is a plain FP8 outer product.

One rounding before the accumulator

Since revision 1.13 the specification scales the exact sum: the four products add up without loss in fixed point, the sum is multiplied by 2^(a + b - 254) for scales a and b, and only then rounded to a single. The old element is added with a second rounding, both to nearest even. With 2^6 (68H) and 2^-9 (01H) in A’s dword and the same in B’s, the sum is 2^12 + 2^-18, which the rounding cuts to 2^12; with A’s scale for that row at 82H (2^3) and B’s at 7FH, the rounded sum is 2^15.

MXCSR is neither read nor written, and nothing is flagged. E4M3 denormals count at their value, a denormal single in the tile counts as zero, and a scaled sum too small for a normal single becomes zero. E4M3 has no infinity, as TDPHF8PS’s page explains, so the QNaN indefinite FFC00000H comes from an E4M3 NaN (7FH or FFH) among the inputs, a NaN in the tile, or a scale of FFH.

In our builds

GNU as 2.44 and Clang 23.1.2 reject the mnemonic, and neither GCC 14.2.0 nor Clang 23.1.2 has ACE’s _tile_top4mxhf8ps intrinsic. The encoding is EVEX opcode 8Dh in map 0F3A with W0 and the 66 prefix; no prefix, F2 and F3 give TOP4MXBF8PS, TOP4MXBHF8PS and TOP4MXHBF8PS, and opcode 8Fh with F2 is the MX INT8 form TOP4MXBSSPS. The exception class is ACE-E4. No processor at hand has ACE, so this site’s recorded cases include none of TOP4MXHF8PS.

Forms

Every encoding of TOP4MXHF8PS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
TOP4MXHF8PS tmm, zmm, zmm, imm8 64-bit mode only TOP4MXHF8PS_TMMf32_ZMMhf8_ZMMhf8_IMM8EVEX.512.66.0F3A.W0 8D /r ibACE v1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

on = xcr0 if cr4 >> 18 & 1 else 0    # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 0xB != 0xB:            # TILECFG, TILEDATA, SCALEDATA
    fault(UD)
if on & 0xE6 != 0xE6:                # AVX-512's state, AVX's and
    fault(UD)                        # SSE's
if palette != 2:                     # ACE's palette alone
    fault(UD)
if cr0 >> 3 & 1 or xfd >> 18 & 1:    # CR0.TS, or the OS keeps the
    fault(NM)                        # tiles from this thread
ga = imm8 & 3                        # the group of A's scales
gb = imm8 >> 3 & 3                   # and of B's
for i in range(16):                  # row i: dword i of zmm2
    sa = bsr0.b[64 + 4 * i + ga]     # 2^(sa - 127)
    for j in range(16):              # column j: dword j of zmm3
        sb = bsr0.b[4 * j + gb]
        s = 0                        # the exact sum
        for k in range(4):
            a = zmm2.hf8[4 * i + k]
            b = zmm3.hf8[4 * j + k]
            p = mul_exact(a, b)
            s = add_exact(s, p)
        c = tmm1.row[i].f32[j]
        r = round_ftz(s, sa + sb - 254)
        t = round_ftz(add_exact(c, r), 0)
        if sa == 0xFF or sb == 0xFF:  # a scale that is a NaN
            t = 0xFFC00000           # the QNaN indefinite
        tmm1.row[i].d[j] = t

Not run on a processor: none of these processors has ACE.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
TOP4MXHF8PS tmm, zmm, zmm, imm8 64-bit mode only
tmmexplicitread, write
zmmexplicitread
zmmexplicitread
imm8explicitread
BSR0implicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
ACE-E4

Attributes

What else XED records about the forms. How to read.

All forms
may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
ACE_1

ACE v1
CPUID.(EAX=07H,ECX=1):ECX[11] ACE
CPUID.(EAX=1DH,ECX=2):EAX[7:0] ≥ 1 ACE version

None in XED’s chip model, which lists these instructions only under its placeholder for future processors.

More ACE instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.