TPAUSE

TPAUSE is a timed PAUSE: it lets the core rest until the time-stamp counter reaches the deadline in EDX:EAX, with no monitored address involved. Where UMWAIT waits for a store to one location, TPAUSE suits a loop that polls something no monitor can watch, several flags or a device register, at a known interval; Intel’s optimization manual notes that it does not depend on how many sources of events there are (Section 3.13.1.3). Like UMWAIT it needs WAITPKG (CPUID leaf 07H, ECX bit 5) and runs at any privilege level.

Same rules as UMWAIT#

The two share their operands and their limits, which the UMWAIT page describes in full:

• the deadline is an absolute TSC value, so a program adds its delay to a fresh RDTSC reading;
• bit 0 of the register operand chooses C0.1 (1, quicker to wake) or C0.2 (0, deeper, and better for the other hardware thread of the core); any other bit raises #GP;
• the operating system’s cap in IA32_UMWAIT_CONTROL may end the wait first, and CF = 1 says so; OF, SF, ZF, AF and PF are cleared;
• with CR4.TSD set it raises #GP outside ring 0.

An interrupt ends the wait even when IF is clear; execution then goes on after TPAUSE, and the interrupt is taken when IF allows. Other events may end it early too, so a TPAUSE loop rereads the TSC and what it polls instead of counting iterations.

Why not PAUSE#

The PAUSE page shows how much one PAUSE’s delay varies between processors, so a loop of PAUSEs waits a different time on each. TPAUSE waits by the clock instead, and lets the core save power or give its resources to the other thread while it does. Intel’s optimization manual recommends UMWAIT, TPAUSE and PAUSE in place of active spinning on its hybrid processors, to give the scheduler better hints (Section 2.3.3).

_tpause(control, deadline) needs -mwaitpkg or an -march such as alderlake or sapphirerapids; GCC 14 and Clang 23 at -O2 emit TPAUSE and return CF with SETC or SETB. Its encoding, 66 0F AE /6, is CLWB’s with a register in place of the memory operand; without the 66, that register form is MFENCE. No AMD processor in this site’s data has WAITPKG, so Zen 5 recorded no cases.

In the optimization guide

What the optimization guide says about TPAUSE, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

• Hybrid processors: Intel advises against pinning threads to cores and for waiting with UMWAIT, TPAUSE or PAUSE. sources differ

Golden Cove and Raptor Cove

• Threads and hybrid parts: On Alder Lake and Raptor Lake, Thread Director tells the operating system how each thread would fare on either kind of core. sources differ
• Threads and hybrid parts: Two AMX threads on one core, or an AMX thread beside another busy thread, slow each other down.

Tremont

• Instruction set and Lakefield: Tremont adds UMWAIT, TPAUSE, CLWB, CLDEMOTE and the direct stores, which GCC enables for it. sources differ

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

c = src.read()                   # bit 0: 1 for C0.1, which wakes
if c & ~1:                       # sooner; 0 for C0.2, which saves
    fault(GP, 0)                 # more, unless the OS forbids it
if CPL > 0 and cr4 >> 2 & 1:     # CR4.TSD, as for RDTSC
    fault(GP, 0)
t = edx << 32 | eax              # rests until the TSC reaches t or
                                 # an event comes
cf = os_timeout(t)               # 1 when the OS's limit came first
of = sf = zf = af = pf = 0

Operands

Flags

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More WAITPKG instructions

• UMONITOR
• UMWAIT