x86-64.net

Instruction

TZCNT

Counts the trailing zero bits of an operand; APX adds a form that leaves the flags unchanged.

Extensions
Forms
6 (2 Legacy, 4 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of TZCNT that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
TZCNT r16/32/64, m16/32/64 TZCNT_GPRv_MEMvF3 0F BC /rBMI1
TZCNT r16/32/64, r16/32/64 TZCNT_GPRv_GPRvF3 0F BC /rBMI1
TZCNT r16/32/64, r16/32/64 TZCNT_GPRv_GPRv_APXEVEX.LLZ.NP.MAP4.SCALABLE F4 /rAPX_F + BMI1
TZCNT r16/32/64, m16/32/64 TZCNT_GPRv_MEMv_APXEVEX.LLZ.NP.MAP4.SCALABLE F4 /rAPX_F + BMI1
TZCNT r16/32/64, r16/32/64 NF TZCNT_GPRv_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE F4 /r NF=1APX_F + APX_NCI_NDD_NF + BMI1
TZCNT r16/32/64, m16/32/64 NF TZCNT_GPRv_MEMv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE F4 /r NF=1APX_F + APX_NCI_NDD_NF + BMI1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
BMI1

BMI1
CPUID.(EAX=07H,ECX=0):EBX[3] BMI1

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill

Note: XED's Piledriver adds TBM and FMA to Bulldozer but not BMI1, and its Zen chips inherit that gap; GCC's -march=bdver2 and -march=znver1 and later include BMI1.

APX_F_BMI1

APX_F + BMI1
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=07H,ECX=0):EBX[3] BMI1

Nova Lake, Diamond Rapids
APX_F_BMI1_N3

APX_F + APX_NCI_NDD_NF + BMI1
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=29H,ECX=0):EBX[0] APX_NCI_NDD_NF
CPUID.(EAX=07H,ECX=0):EBX[3] BMI1

Nova Lake, Diamond Rapids

More BMI1 instructions

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.