Extensions
Forms
2 (2 Legacy)
Data
Intel XED v2026.08.23

UCOMISD is the quiet version of COMISD: it compares the low doubles of two operands and sets ZF, PF and CF the same way, all three for an unordered result, but raises the invalid-operation exception only when an input is a signaling NaN, not a quiet one. COMISD’s page explains how the flags map to condition codes, why compilers swap the operands for “less than”, and the one case, equality, where Clang bypasses both instructions for a mask built with CMPEQSD or CMPNEQSD.

On Zen 5, in a masked case with DAZ set, a quiet NaN compared against a signaling NaN, read from memory, set ZF, PF and CF (unordered) and IE, since one input was signaling; in a masked, clean case, comparing a non-NaN value against itself gave “equal” with PF clear, ordered as any repeated value must be, unlike the self-compare of a NaN that isnan() relies on.

What compiled code shows most

GCC 14 and Clang 23 at -O2 use UCOMISD for isless(), isgreater() and the other quiet macros, and for isunordered(), which both compile to ucomisd xmm0, xmm1 and SETP. isnan(x) is ucomisd xmm0, xmm0 and SETP in both, since only a NaN is unordered with itself. GCC also uses UCOMISD for == and !=, testing ZF and PF after it as COMISD’s page describes; Clang instead builds a mask with CMPEQSD or CMPNEQSD for those two, unless -ffp-exception-behavior=strict is given, when it falls back to UCOMISD like GCC.

UCOMISD writes no XMM register, and its memory operand is eight bytes at any alignment. VUCOMISD is the VEX and EVEX form (the EVEX one can suppress all exceptions with {sae}), and UCOMISS is the version for singles.

Forms

Every encoding of UCOMISD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
UCOMISD xmm, m64 UCOMISD_XMMsd_MEMsd66 0F 2E /rSSE2
UCOMISD xmm, xmm UCOMISD_XMMsd_XMMsd66 0F 2E /rSSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The low doubles of the two sources are compared, and the result sets ZF, PF and CF.
UCOMISD: the low element to the flagsThe flags come from double 0 of xmm1 and xmm2. RFLAGS: CF, PF, ZF.01xmm1aZFPFCFRFLAGS01xmm2or m64b

The flags come from double 0 of xmm1 and xmm2. RFLAGS: CF, PF, ZF.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = ucomi(xmm1.f64[0], src2.f64[0])  # 0 >, 1 <, 2 =, 3 unordered
zf = x in (2, 3)
pf = x == 3
cf = x in (1, 3)
of = sf = af = 0
# only an SNaN raises IE

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
UCOMISD xmm, xmm/m64
xmmexplicitread
xmm/m64explicitread
RFLAGSimplicitwrite

Flags

M modified, 0 cleared; blank: not affected. How to read.
OFSFZFAFPFCF
All forms
00M0MM

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
SSE_TYPE_3

Attributes

What else XED records about the forms. How to read.

All forms
follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to UCOMISD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_ucomieq_sd int _mm_ucomieq_sd(__m128d __a, __m128d __b)

UCOMISD xmm, xmm Legacy -msse2

_mm_ucomige_sd int _mm_ucomige_sd(__m128d __a, __m128d __b)

UCOMISD xmm, xmm Legacy -msse2

_mm_ucomigt_sd int _mm_ucomigt_sd(__m128d __a, __m128d __b)

UCOMISD xmm, xmm Legacy -msse2

_mm_ucomile_sd int _mm_ucomile_sd(__m128d __a, __m128d __b)

UCOMISD xmm, xmm Legacy -msse2

_mm_ucomilt_sd int _mm_ucomilt_sd(__m128d __a, __m128d __b)

UCOMISD xmm, xmm Legacy -msse2

_mm_ucomineq_sd int _mm_ucomineq_sd(__m128d __a, __m128d __b)

UCOMISD xmm, xmm Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
SSE2

SSE2
CPUID.01H:EDX[26] SSE2

Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-733 (UCOMISD)
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  6. AMD64 Architecture Programmer's Manual, Volume 4: 128-Bit and 256-Bit Media Instructions (26568, rev. 3.25, November 2021), Wayback Machine copy of AMD's PDF
  7. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.